Recent questions tagged goclasses-digital-logic-practice-questions

A ring counter and a Johnson counter are both built using $4$ flip-flops. Assuming normal operation, how many states are produced by the ring counter and the Johnson coun...

Which statement is correct for a synchronous counter?All flip-flops receive the same clock signal, and the next state is decided using combinational logic Only the first ...

A $3$-bit counter is designed to count through the states $0,1,2,3,4,5$ and then return to $0$. What is the modulus of the counter, and how many states are unused?Modulo-...

A 3-bit ripple up counter starts from state $000$. What will be its state after $5$ clock pulses?$011$ $100$ $101$ $110$

Which statement correctly describes an asynchronous or ripple counter?All flip-flops receive the same clock signal directly The output of one flip-flop is used as the clo...

A clock signal of frequency $16$ kHz is applied to a chain of T flip-flops. Each T flip-flop divides the frequency by $2$. How many T flip-flops are required to obtain an...

How many states are present in a $5$-bit binary counter, and what is the maximum decimal count value?$16$ states, maximum count $15$ $32$ states, maximum count $31$ $32$ ...

A $4$-bit right shift register initially contains $1011$. Serial input enters from the left side. The serial input values applied in two consecutive clock pulses are $0$ ...

How many flip-flops are required to construct a $12$-bit register?$6$ $8$ $12$ $24$

Which statement correctly defines a register?A register is a group of flip-flops used to store binary information A register is a combinational circuit used only for arit...

How does a master-slave JK flip-flop help in avoiding race around condition?It removes the clock input completely It uses two latches controlled in opposite clock phases ...

In a level-triggered JK flip-flop, race around condition occurs when:$\mathrm{J}=0,\mathrm{K}=0$ and clock pulse width is very small $\mathrm{J}=1,\mathrm{K}=1$ and clock...

Which statement correctly describes the difference between a level-sensitive D latch and an edge-triggered D flip-flop?A level-sensitive latch responds throughout the act...

A flip-flop has active-low direct inputs $\mathrm{Preset}_n$ and $\mathrm{Clear}_n$. What will be the output when $\mathrm{Preset}_n=1$ and $\mathrm{Clear}_n=0$?$\mathrm{...

Which statement correctly describes preset and clear inputs in a flip-flop?Preset forces the flip-flop to $0$, and clear forces the flip-flop to $1$ Preset forces the fli...

A T flip-flop is to be converted into a D flip-flop. Which input equation should be applied to the T input?$T=D\oplus Q_n$ $T=D$ $T=DQ_n$ $T=D+Q_n$

An SR flip-flop is to be converted into a T flip-flop. Which pair of input equations correctly makes the SR flip-flop behave like a T flip-flop?$S=TQ_n',\ R=TQ_n$ $S=TQ_n...

A D flip-flop is to be converted into a JK flip-flop. Which expression should be connected to the D input?$D=JQ_n'+K'Q_n$ $D=JQ_n+KQ_n'$ $D=J+K+Q_n$ $D=JKQ_n$

A D flip-flop is to be converted into a T flip-flop. Which input equation should be applied to the D input?$D=T\oplus Q_n$ $D=TQ_n$ $D=T+Q_n$ $D=T'Q_n$

A JK flip-flop is to be converted into a T flip-flop. What should be the input connections for J and K?$J=T,\ K=T$ $J=T,\ K=T'$ $J=T',\ K=T$ $J=0,\ K=T$

A positive-edge triggered T flip-flop has initial output $Q=1$. The value of $T$ at five consecutive positive clock edges is:$$1,0,1,1,0$$What will be the output sequence...

For a JK flip-flop, what should be the values of $J$ and $K$ to change the state from $Q_n=0$ to $Q_{n+1}=1$?$J=0,K=X$ $J=1,K=X$ $J=X,K=1$ $J=X,K=0$

Which expression correctly represents the characteristic equation of a JK flip-flop?$Q_{n+1}=JQ_n'+K'Q_n$ $Q_{n+1}=JQ_n+KQ_n'$ $Q_{n+1}=J+K+Q_n$ $Q_{n+1}=JKQ_n$

A positive-edge triggered D flip-flop has initial output $Q=0$. The value of $D$ at three consecutive positive clock edges is $1,0,1$. What will be the output sequence af...

A positive-edge triggered D flip-flop has feedback connection $D=Q_n'$. If the initial value is $Q_0=0$, what will be the output sequence after four positive clock edges?...

For an active-high SR flip-flop, which expression correctly represents the next state?$Q_{n+1}=S+R'Q_n$ $Q_{n+1}=R+SQ_n$ $Q_{n+1}=S'R+Q_n$ $Q_{n+1}=SR+Q_n$

For a gated SR latch with active-high clock, which condition is invalid when clock $=1$?$S=0,R=0$ $S=1,R=0$ $S=0,R=1$ $S=1,R=1$

In a gated SR latch, the clock input is $0$. If $S=1$ and $R=0$, what will happen to the latch output?It will be set to $1$ It will be reset to $0$ It will hold the previ...

A clock signal has time period $T=20$ ns. The signal remains high for $8$ ns in every cycle. What are the frequency and duty cycle of the clock?$25$ MHz, $40$% $50$ MHz, ...

In basic sequential circuits, a flip-flop can be understood as:A combinational circuit without memory A latch controlled by a clock signal A decoder controlled by a multi...