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Recent questions tagged goclasses-digital-logic-practice-questions
7
7 votes
1
1 answer
204
204 views
GO Classes DPP | GATE CS | Digital Logic | NAND-based SR Latch
For an SR latch using NAND gates, the inputs are active-low. Which option correctly describes the latch behavior?$S=0,R=1$ sets the latch, $S=1,R=0$ resets the latch, $S=...
GO Classes
204
views
asked
Jun 22
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-304
goclasses-digital-logic-practice-questions
latch
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6
6 votes
1
1 answer
173
173 views
GO Classes DPP | GATE CS | Digital Logic | NOR-based SR Latch
In a NOR-based SR latch, why is the input condition $S=1,R=1$ considered invalid?Because both outputs become $1$ Because both outputs become $0$, so $Q$ and $Q'$ are not ...
GO Classes
173
views
asked
Jun 22
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-304
goclasses-digital-logic-practice-questions
latch
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7
7 votes
1
1 answer
190
190 views
GO Classes DPP | GATE CS | Digital Logic | NOR-based SR Latch
For an active-high SR latch using NOR gates, which option correctly describes the latch behavior?$S=1,R=0$ sets the latch, $S=0,R=1$ resets the latch, $S=0,R=0$ holds the...
GO Classes
190
views
asked
Jun 22
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-304
goclasses-digital-logic-practice-questions
latch
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4
4 votes
1
1 answer
191
191 views
GO Classes DPP | GATE CS | Digital Logic | Memory & Feedback
In a sequential circuit, the circuit is able to remember previous output mainly because of:Encoder Decoder Feedback or memory element Multiplexer
GO Classes
191
views
asked
Jun 22
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-304
goclasses-digital-logic-practice-questions
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5
5 votes
1
1 answer
215
215 views
GO Classes DPP | GATE CS | Digital Logic | Combinational vs Sequential Circuits
Which statement correctly differentiates a combinational circuit from a sequential circuit?A combinational circuit depends only on current inputs, while a sequential circ...
GO Classes
215
views
asked
Jun 22
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
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goclasses-digital-logic-practice-questions
combinational-circuit
sequential-circuit
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6
6 votes
1
1 answer
221
221 views
GO Classes DPP | GATE CS | Digital Logic | Functional Completeness
A Boolean operator $\odot$ is defined by the following truth table:\[\begin{array}{|c|c|c|}\hlineA & B & A \odot B \\\hline0 & 0 & 1 \\0 & 1 & 0 \\1 & 0 & 0 \\1 & 1 & 0\\...
GO Classes
221
views
asked
Jun 20
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-303
goclasses-digital-logic-practice-questions
functional-completeness
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8
8 votes
1
1 answer
203
203 views
GO Classes DPP | GATE CS | Digital Logic | Incomplete Set
Which of the following statements is correct about the set {XOR, NOT}?It is functionally complete because it contains NOT It is functionally complete because XOR can prod...
GO Classes
203
views
asked
Jun 20
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-303
goclasses-digital-logic-practice-questions
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4
4 votes
1
1 answer
188
188 views
GO Classes DPP | GATE CS | Digital Logic | NAND as a Universal Gate
Let $A \uparrow B$ denote the NAND operation, where:$A \uparrow B=(AB)'$Which set of expressions correctly proves that NAND alone is functionally complete?$A'=A\uparrow A...
GO Classes
188
views
asked
Jun 20
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-303
goclasses-digital-logic-practice-questions
nand
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5
5 votes
1
1 answer
197
197 views
GO Classes DPP | GATE CS | Digital Logic | Minterm Expansion
For a Boolean function $f(A,B,C)=\Sigma m(1,2,5,7)$, which expression correctly represents the standard SOP form?$f=A'B'C+A'BC'+AB'C+ABC$ $f=A'B'C'+A'BC+AB'C'+ABC'$ $f=A'...
GO Classes
197
views
asked
Jun 20
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-303
goclasses-digital-logic-practice-questions
minterms
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7
7 votes
1
1 answer
207
207 views
GO Classes DPP | GATE CS | Digital Logic | Functional Completeness
A set of Boolean operations is called functionally complete if:It contains only AND and OR gates It can be used to express every Boolean function It contains XOR operatio...
GO Classes
207
views
asked
Jun 20
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-303
goclasses-digital-logic-practice-questions
functional-completeness
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4
4 votes
1
1 answer
188
188 views
GO Classes DPP | GATE CS | Digital Logic | Carry Look-Ahead Equation
In a carry look-ahead adder,$C_{i+1}=G_i+P_iC_i$Which expression correctly represents $C_3$ in terms of $G_0,G_1,G_2,P_0,P_1,P_2$ and $C_0$?$C_3=G_2+P_2G_1+P_2P_1G_0+P_2P...
GO Classes
188
views
asked
Jun 19
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-302
goclasses-digital-logic-practice-questions
carry-look-ahead-adder
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2
2 votes
1
1 answer
157
157 views
GO Classes DPP | GATE CS | Digital Logic | Generate and Propagate
For a carry look-ahead adder, let$G_i=A_iB_i$and$P_i=A_i\oplus B_i$For bit position $i$, what do $G_i=1$ and $P_i=1$ represent?$G_i=1$ means carry is propagated, and $P_i...
GO Classes
157
views
asked
Jun 19
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-302
goclasses-digital-logic-practice-questions
carry-look-ahead-adder
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3
3 votes
1
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163
163 views
GO Classes DPP | GATE CS | Digital Logic | Carry Propagation
In a ripple carry adder, which condition causes a carry to propagate through bit position $i$?$A_i=0$ and $B_i=0$ $A_i=1$ and $B_i=1$ $A_i\oplus B_i=1$ $A_iB_i=1$
GO Classes
163
views
asked
Jun 19
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-302
goclasses-digital-logic-practice-questions
ripple-carry-adder
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4
4 votes
1
1 answer
177
177 views
GO Classes DPP | GATE CS | Digital Logic | Ripple Carry Delay
A $4$-bit ripple carry adder is made using full adders. For each full adder, carry propagation delay from $C_{in}$ to $C_{out}$ is $2$ $\text{ns}$, and sum delay from $C_...
GO Classes
177
views
asked
Jun 19
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-302
goclasses-digital-logic-practice-questions
ripple-carry-adder
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5
5 votes
1
1 answer
152
152 views
GO Classes DPP | GATE CS | Digital Logic | Propagation Delay
A circuit has two gates in series. First, $X=AB$ is produced using an AND gate with delay $4$ $\text{ns}$. Then, $F=X+C$ is produced using an OR gate with delay $3$ $\tex...
GO Classes
152
views
asked
Jun 19
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-302
goclasses-digital-logic-practice-questions
propagation-delay
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5
5 votes
2
2 answers
204
204 views
GO Classes DPP | GATE CS | Digital Logic | Full Adder Carry
In a full adder, the carry output is $C_{out}=AB+C_{in}(A\oplus B)$. For which input combinations does the full adder generate carry independent of $C_{in}$?$A=0,B=0$ $A=...
GO Classes
204
views
asked
Jun 18
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-301
goclasses-digital-logic-practice-questions
full-adder
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3
3 votes
1
1 answer
156
156 views
GO Classes DPP | GATE CS | Digital Logic | Ripple Carry Addition
A $4$-bit ripple carry adder adds $A=1011$ and $B=0111$ with initial carry $C_0=0$. What are the final $4$-bit sum and final carry?Sum $=0010$, $C_4=1$ Sum $=10010$, $C_4...
GO Classes
156
views
asked
Jun 18
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-301
goclasses-digital-logic-practice-questions
ripple-carry-adder
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5
5 votes
1
1 answer
181
181 views
GO Classes DPP | GATE CS | Digital Logic | Two-bit Binary Adder
Two unsigned $2$-bit numbers $A_1A_0$ and $B_1B_0$ are added with no input carry. Which implementation and equations are correct?LSB uses half adder: $S_0=A_0\oplus B_0$,...
GO Classes
181
views
asked
Jun 18
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-301
goclasses-digital-logic-practice-questions
adder
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4
4 votes
1
1 answer
166
166 views
GO Classes DPP | GATE CS | Digital Logic | Full Adder Truth Table
For a full adder with inputs $A$, $B$, and $C_{in}$, for which input combinations are $S=0$ and $C_{out}=1$?$000,111$ $011,101,110$ $001,010,100$ $011,101,111$
GO Classes
166
views
asked
Jun 18
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-301
goclasses-digital-logic-practice-questions
adder
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4
4 votes
1
1 answer
155
155 views
GO Classes DPP | GATE CS | Digital Logic | Full Adder using Half Adders
A full adder is implemented using two half adders and one OR gate. The first half adder takes inputs $A$ and $B$. The second half adder takes the first sum output and $C_...
GO Classes
155
views
asked
Jun 18
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-301
goclasses-digital-logic-practice-questions
adder
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2
2 votes
1
1 answer
219
219 views
GO Classes DPP | GATE CS | Digital Logic | Priority Encoder
A $4:2$ priority encoder has active-high inputs $\mathrm{D}_0,\mathrm{D}_1,\mathrm{D}_2,\mathrm{D}_3$, where $\mathrm{D}_3$ has the highest priority and $\mathrm{D}_0$ ha...
GO Classes
219
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
priority-encoder
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6
6 votes
2
2 answers
232
232 views
GO Classes DPP | GATE CS | Digital Logic | Binary Encoder
For a $4:2$ binary encoder with active-high inputs $\mathrm{I}_0,\mathrm{I}_1,\mathrm{I}_2,\mathrm{I}_3$ and outputs $\mathrm{Y}_1,\mathrm{Y}_0$, assume exactly one input...
GO Classes
232
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
encoder
binary-encoder
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4
4 votes
2
2 answers
216
216 views
GO Classes DPP | GATE CS | Digital Logic | DEMUX
A $1:4$ DEMUX has data input $\mathrm{D}$ and select lines $\mathrm{S}_1,\mathrm{S}_0$. Which of the following output equations is correct?$\mathrm{Y}_0=\mathrm{S}_1\math...
GO Classes
216
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
demux
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6
6 votes
2
2 answers
282
282 views
GO Classes DPP | GATE CS | Digital Logic | MUX with Enable
A $2:1$ MUX has inputs $\mathrm{I}_0,\mathrm{I}_1$, select line $\mathrm{S}$, and active-low enable input $\mathrm{E}$. When $\mathrm{E}=1$, the output is $0$. When $\mat...
GO Classes
282
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
multiplexer
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3
3 votes
2
2 answers
269
269 views
GO Classes DPP | GATE CS | Digital Logic | Large MUX using Smaller MUX
How many $4:1$ MUXes are required to implement one $16:1$ MUX?$4$ $5$ $6$ $8$
GO Classes
269
views
asked
Jun 17
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-300
goclasses-digital-logic-practice-questions
multiplexer
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11
11 votes
2
2 answers
308
308 views
GO Classes DPP | GATE CS | Digital Logic | MUX Realization
The Boolean function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C},\mathrm{D})=\Sigma _m(2,3,4,6,9,10,12,13,14,15)$ is to be implemented using a $4:1$ MUX with select line...
GO Classes
308
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
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6
6 votes
1
1 answer
189
189 views
GO Classes DPP | GATE CS | Digital Logic | Cascaded MUX
Two $2:1$ MUXes are connected as follows :The first MUX has select line $\mathrm{A}$, input $\mathrm{I}_0=\mathrm{B}$, input $\mathrm{I}_1=\mathrm{C}$, and output $\mathr...
GO Classes
189
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
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4
4 votes
1
1 answer
170
170 views
GO Classes DPP | GATE CS | Digital Logic | MUX Output
A $4:1$ MUX has select lines $\mathrm{S}_1=\mathrm{R}$ and $\mathrm{S}_0=\mathrm{S}$, where $\mathrm{R}$ is MSB and $\mathrm{S}$ is LSB. The data inputs are $\mathrm{I}_0...
GO Classes
170
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
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5
5 votes
1
1 answer
200
200 views
GO Classes DPP | GATE CS | Digital Logic | MUX
The function $\mathrm{F}(\mathrm{A},\mathrm{B})=\mathrm{A}\oplus\mathrm{B}$ is implemented using an $8:1$ MUX. The select lines are connected as $\mathrm{S}_2=0$, $\mathr...
GO Classes
200
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
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7
7 votes
2
2 answers
218
218 views
GO Classes DPP | GATE CS | Digital Logic | MUX
The Boolean function $\mathrm{F}(\mathrm{A},\mathrm{B},\mathrm{C})=\Sigma _m(1,2,4,7)$ is to be implemented using a $2:1$ MUX with select line $\mathrm{S}=\mathrm{A}$. Wh...
GO Classes
218
views
asked
Jun 16
Digital Logic
goclasses
goclasses-cs-dpp
digital-logic
goclasses-cs-dpp-day-299
goclasses-digital-logic-practice-questions
multiplexer
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