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Recent questions tagged adder
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Morris Mano Edition 3 Exercise 5 Question 12 (Page No. 199)
It is necessary to design a decimal Adder for two digits represented in Excess3 code. Show that the correction after adding the two digits with a fourbit binary adder is as follows. The output carry is equal to the carry from ... output carry is 0 then add 1101. construct a fourbit decimal adder using two 4bit adders and an inverter..
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Apr 3
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Morris Mano Edition 3 Exercise 5 Question 11 (Page No. 198)
Construct a 4digit BCD addersubtractor using 4 BCD adders. Use the Block diagram for each component, showing only inputs and outputs.
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Apr 3
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Morris Mano Edition 3 Exercise 5 Question 9 (Page No. 198)
How many Unused Combinations are there in BCD adder?
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Digital Logic
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Morris Mano Edition 3 Exercise 5 Question 8 (Page No. 198)
Derive the twolevel Boolean expression for the output carry $C _5$ shown in the lookahead carry generator of the figure
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Apr 3
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Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
Assume that the EXCLUSIVEOR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the fourbit adder of the figure given below?
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Apr 3
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Digital Logic
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6
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
(a) Redefine the carry propagate and carry generate as follows: $P _i = A _i + B _ i$ $G _i = A _iB _i$ ... circuit for this IC. [Hint: use the equation substitution method and ANDORINVERT funtion given in part (a) for $C _{i+1}$
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Morris Mano Edition 3 Exercise 5 Question 5 (Page No. 198)
Using the ANDORInvert implementation procedure, show that the output carry in full adder can be expressed as $C _{i+1} = G _i + P _iC _i = (G _i'P _i + G _i'C _i')'$ IC type 74182 is a lookahead carry generator MSI ... $C _1'$).
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Morris Mano Edition 3 Exercise 5 Question 4 (Page No. 197)
The addersubtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S _2 S _1$ and $C _5$. M A B 0 0111 0110 0 1000 1001 1 0101 1000 1 0000 1010
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Morris Mano Edition 3 Exercise 5 Question 3 (Page No. 197)
The addersubtractor of the figure is used to subtract the following unsigned 4bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the circuit $?$ what are the binary values of the five outputs of the circuit$?$ Explain How the output is related to the operation of 6 – 9.
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Apr 3
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Digital Logic
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Morris Mano Edition 3 Exercise 5 Question 2 (Page No. 197)
Construct a BCDtoExcess3code converter with a 4bit adder.remember that the Excess3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be done to change the circuit to an excess3toBCDcode converter
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Apr 3
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Digital Logic
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11
Morris Mano Edition 3 Exercise 5 Question 1 (Page No. 197)
Construct a 16bit parallel adder with four MSI circuits, each containing a fourbit parallel adder. Use a block diagram with 9 inputs and five outputs for each 4bit adder. Show how the carries are connected between the MSI circuits.
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Apr 3
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Nielit STA 2018
Minimum number of Full adders and half adders required by the BCD adder to add two decimal digits.
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Dec 5, 2018
in
Digital Logic
by
Robert Soram
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39
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52
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Full adder
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Nov 15, 2018
in
Digital Logic
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Na462
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14
MadeEasy Workbook: Digital Logic  Adder
x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d then what will be the maximum Delay of carry look ahead adder circuit? N2 Kd Nkd Nd
asked
Nov 12, 2018
in
Digital Logic
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shgarg
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madeeasytestseries
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15
Self Doubt
Suppose we are using 4bit carry lookahead adder modules to build a 64 bit adder with twolevel carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worstcase delay of the 64bit adder will be ……….. nanoseconds.
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Nov 7, 2018
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jatin khachane 1
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16
Gateforum Test Series: Digital Logic  Adder
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Nov 6, 2018
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Digital Logic
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Gupta731
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17
Full adder
asked
Oct 1, 2018
in
Digital Logic
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Na462
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18
Sums on Adder
$1)$3bit ripple adder, which adds two 3bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, ... both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?
asked
Aug 30, 2018
in
Digital Logic
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srestha
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19
Adder delay
A full adder circuit takes 20 ns to generate the carryout bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec. Usual Solution given The ... calculate the total time taken to perform one round of four bit addition. Right? (Similar old question: https://gateoverflow.in/83500/digitals)
asked
Aug 19, 2018
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GateAspirant999
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20
Doubt
How to check whether there is overflow in nbit parallel adder?
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Aug 3, 2018
in
Digital Logic
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aditi19
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adder
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21
doubt
How to Calculate Propagation Delay In Carry Look Ahead Adder.
asked
Jul 18, 2018
in
Digital Logic
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bhavnakumrawat5
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165
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carry
look
ahead
adder
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22
gate 2004
A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??
asked
May 27, 2018
in
Digital Logic
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BASANT KUMAR
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115
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digitallogic
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0
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23
Adder
One ripple carry adder is adding two nbit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
asked
May 21, 2018
in
Digital Logic
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srestha
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24
Digital Logic
Please elaborate your answer.
asked
Jan 9, 2018
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Digital Logic
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gauravkc
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25
CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
asked
Dec 30, 2017
in
Digital Logic
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AnilGoudar
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124
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digitallogic
carrygenerator
adder
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26
MadeEasy Test Series: Digital Logic  Adder
A 1bit full adder circuit takes 5 ns to generate the carryout bit and 10 ns for the sumbit. When 4, 1bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.
asked
Dec 4, 2017
in
Digital Logic
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shivangi5
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27
MadeEasy Test Series: Digital Logic  Adder
asked
Dec 3, 2017
in
Digital Logic
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Jaspreet Kaur Bains
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+3
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28
Modified GATE 2003 question
Consider this GATE 2003 question: https://gateoverflow.in/937/gate200346 Here, instead of XOR gates we had OR gates, then which of the following operations can we perform? $A + B, A  B\ and\ A + 1$
asked
Nov 3, 2017
in
CO & Architecture
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Rishabh Gupta 2
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191
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29
MadeEasy WorkBook: Digital Logic  Adder
asked
Oct 27, 2017
in
Digital Logic
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charul
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30
GATE2003
asked
Oct 22, 2017
in
Digital Logic
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chetan raghav
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