The Gateway to Computer Science Excellence
For all GATE CSE Questions
Toggle navigation
Facebook Login
or
Email or Username
Password
Remember
Login
Register

I forgot my password
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
Recent questions tagged adder
0
votes
0
answers
1
Morris Mano Edition 3 Exercise 5 Question 12 (Page No. 199)
It is necessary to design a decimal Adder for two digits represented in Excess3 code. Show that the correction after adding the two digits with a fourbit binary adder is as follows. The output carry is equal to the carry from ... output carry is 0 then add 1101. construct a fourbit decimal adder using two 4bit adders and an inverter..
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

49
views
digitallogic
combinationalcircuits
adder
0
votes
0
answers
2
Morris Mano Edition 3 Exercise 5 Question 11 (Page No. 198)
Construct a 4digit BCD addersubtractor using 4 BCD adders. Use the Block diagram for each component, showing only inputs and outputs.
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

16
views
digitallogic
combinationalcircuits
adder
0
votes
0
answers
3
Morris Mano Edition 3 Exercise 5 Question 9 (Page No. 198)
How many Unused Combinations are there in BCD adder?
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

11
views
digitallogic
combinationalcircuits
adder
0
votes
0
answers
4
Morris Mano Edition 3 Exercise 5 Question 8 (Page No. 198)
Derive the twolevel Boolean expression for the output carry $C _5$ shown in the lookahead carry generator of the figure
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

9
views
digitallogic
combinationalcircuits
adder
0
votes
0
answers
5
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
Assume that the EXCLUSIVEOR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the fourbit adder of the figure given below?
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

17
views
digitallogic
combinationalcircuits
adder
0
votes
0
answers
6
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
(a) Redefine the carry propagate and carry generate as follows: $P _i = A _i + B _ i$ $G _i = A _iB _i$ ... circuit for this IC. [Hint: use the equation substitution method and ANDORINVERT funtion given in part (a) for $C _{i+1}$
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

34
views
digitallogic
combinationalcircuits
adder
carrygenerator
0
votes
0
answers
7
Morris Mano Edition 3 Exercise 5 Question 5 (Page No. 198)
Using the ANDORInvert implementation procedure, show that the output carry in full adder can be expressed as $C _{i+1} = G _i + P _iC _i = (G _i'P _i + G _i'C _i')'$ IC type 74182 is a lookahead carry generator MSI ... $C _1'$).
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

13
views
digitallogic
combinationalcircuits
adder
carrygenerator
0
votes
0
answers
8
Morris Mano Edition 3 Exercise 5 Question 4 (Page No. 197)
The addersubtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S _2 S _1$ and $C _5$. M A B 0 0111 0110 0 1000 1001 1 0101 1000 1 0000 1010
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

79
views
digitallogic
combinationalcircuits
adder
digitalcircuits
0
votes
0
answers
9
Morris Mano Edition 3 Exercise 5 Question 3 (Page No. 197)
The addersubtractor of the figure is used to subtract the following unsigned 4bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the circuit $?$ what are the binary values of the five outputs of the circuit$?$ Explain How the output is related to the operation of 6 – 9.
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

18
views
digitallogic
combinationalcircuits
adder
digitalcircuits
+1
vote
0
answers
10
Morris Mano Edition 3 Exercise 5 Question 2 (Page No. 197)
Construct a BCDtoExcess3code converter with a 4bit adder.remember that the Excess3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be done to change the circuit to an excess3toBCDcode converter
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

25
views
digitallogic
combinationalcircuits
adder
digitalcircuits
+1
vote
0
answers
11
Morris Mano Edition 3 Exercise 5 Question 1 (Page No. 197)
Construct a 16bit parallel adder with four MSI circuits, each containing a fourbit parallel adder. Use a block diagram with 9 inputs and five outputs for each 4bit adder. Show how the carries are connected between the MSI circuits.
asked
Apr 3
in
Digital Logic
by
ajaysoni1924
Boss
(
10.5k
points)

43
views
digitallogic
combinationalcircuits
adder
0
votes
1
answer
12
Full adder
asked
Nov 15, 2018
in
Digital Logic
by
Na462
Loyal
(
6.8k
points)

82
views
digitallogic
carrygenerator
adder
fulladder
0
votes
0
answers
13
MadeEasy Workbook: Digital Logic  Adder
x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d then what will be the maximum Delay of carry look ahead adder circuit? N2 Kd Nkd Nd
asked
Nov 12, 2018
in
Digital Logic
by
shgarg
(
21
points)

81
views
digitallogic
adder
madeeasytestseries
0
votes
0
answers
14
Self Doubt
Suppose we are using 4bit carry lookahead adder modules to build a 64 bit adder with twolevel carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worstcase delay of the 64bit adder will be ……….. nanoseconds.
asked
Nov 7, 2018
in
Digital Logic
by
jatin khachane 1
Loyal
(
7.2k
points)

94
views
digitallogic
adder
0
votes
2
answers
15
Gateforum Test Series: Digital Logic  Adder
asked
Nov 6, 2018
in
Digital Logic
by
Gupta731
Active
(
4.7k
points)

65
views
gateforumtestseries
digitallogic
adder
0
votes
2
answers
16
Full adder
asked
Oct 1, 2018
in
Digital Logic
by
Na462
Loyal
(
6.8k
points)

129
views
digitallogic
adder
carrygenerator
+1
vote
2
answers
17
Sums on Adder
$1)$3bit ripple adder, which adds two 3bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, ... both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?
asked
Aug 30, 2018
in
Digital Logic
by
srestha
Veteran
(
117k
points)

318
views
digitallogic
adder
0
votes
1
answer
18
Adder delay
A full adder circuit takes 20 ns to generate the carryout bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec. Usual Solution given The ... calculate the total time taken to perform one round of four bit addition. Right? (Similar old question: https://gateoverflow.in/83500/digitals)
asked
Aug 19, 2018
in
Digital Logic
by
GateAspirant999
Active
(
2.4k
points)

261
views
digitallogic
adder
combinational
digitalcircuits
0
votes
0
answers
19
Doubt
How to check whether there is overflow in nbit parallel adder?
asked
Aug 3, 2018
in
Digital Logic
by
aditi19
Active
(
5k
points)

50
views
adder
0
votes
1
answer
20
gate 2004
A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??
asked
May 27, 2018
in
Digital Logic
by
BASANT KUMAR
Active
(
2.8k
points)

121
views
digitallogic
adder
0
votes
1
answer
21
Adder
One ripple carry adder is adding two nbit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
asked
May 21, 2018
in
Digital Logic
by
srestha
Veteran
(
117k
points)

110
views
digitallogic
carrygenerator
adder
+2
votes
0
answers
22
Digital Logic
Please elaborate your answer.
asked
Jan 9, 2018
in
Digital Logic
by
gauravkc
Loyal
(
7.8k
points)

72
views
digitallogic
adder
+1
vote
1
answer
23
CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
asked
Dec 30, 2017
in
Digital Logic
by
AnilGoudar
Active
(
4.3k
points)

145
views
digitallogic
carrygenerator
adder
0
votes
0
answers
24
Half adders
asked
Dec 5, 2017
in
Digital Logic
by
Parshu gate
Active
(
3.1k
points)

138
views
combinational
digitallogic
adder
0
votes
1
answer
25
MadeEasy Test Series: Digital Logic  Adder
A 1bit full adder circuit takes 5 ns to generate the carryout bit and 10 ns for the sumbit. When 4, 1bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.
asked
Dec 4, 2017
in
Digital Logic
by
shivangi5
Active
(
1.1k
points)

84
views
madeeasytestseries
digitallogic
adder
0
votes
1
answer
26
MadeEasy Test Series: Digital Logic  Adder
asked
Dec 3, 2017
in
Digital Logic
by
Jaspreet Kaur Bains
Junior
(
567
points)

99
views
madeeasytestseries
digitallogic
adder
multiplexer
+4
votes
0
answers
27
Modified GATE 2003 question
Consider this GATE 2003 question: https://gateoverflow.in/937/gate200346 Here, instead of XOR gates we had OR gates, then which of the following operations can we perform? $A + B, A  B\ and\ A + 1$
asked
Nov 3, 2017
in
CO and Architecture
by
Rishabh Gupta 2
Boss
(
17.4k
points)

242
views
gate2003
adder
0
votes
1
answer
28
MadeEasy WorkBook: Digital Logic  Adder
asked
Oct 27, 2017
in
Digital Logic
by
charul
Junior
(
805
points)

156
views
digitallogic
adder
madeeasybooklet
+2
votes
0
answers
29
GATE2003
asked
Oct 22, 2017
in
Digital Logic
by
chetan raghav
(
77
points)

83
views
full
adder
+2
votes
1
answer
30
Digital Systems  Help building a 4 bit Binary adder circuit
asked
Oct 2, 2017
in
Digital Logic
by
Garrett McClure
(
265
points)

420
views
digitallogic
digitalcircuits
adder
Page:
1
2
3
next »
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
OFFICIAL GATE MOCK TEST RELEASED
IIITH: Winter Research Admissions 2019 (For Spring 2020)
TIFR and JEST exam
Minimal Deterministic Finite Automata
To be aware of fake GATE test series
Follow @csegate
Recent questions tagged adder
Recent Blog Comments
What region behind page not found in gate...
Sir can you please suggest some way like how can...
I think it's been refactored...
@ankitgupta.1729 options after JEST for...
@ankitgupta.1729 @arjun sir There is no...
50,651
questions
56,214
answers
194,173
comments
95,424
users