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Recent questions tagged adder

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It is necessary to design a decimal Adder for two digits represented in Excess-3 code. Show that the correction after adding the two digits with a four-bit binary adder is as follows. The output carry is equal to the carry from the binary adder. If the Output carry is 1 ... add 0011. if the output carry is 0 then add 1101. construct a four-bit decimal adder using two 4-bit adders and an inverter..
asked Apr 3, 2019 in Digital Logic ajaysoni1924 239 views
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Assume that the EXCLUSIVE-OR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the four-bit adder of the figure given below?
asked Apr 3, 2019 in Digital Logic ajaysoni1924 235 views
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(a) Redefine the carry propagate and carry generate as follows: $P _i = A _i + B _ i$ $G _i = A _iB _i$ Show that the output carry and output sum of a full adder becomes $C _i{+1} = (C _i'G _i + P _i')' = G _i + P _iC _i$ ... draw the two level look ahead circuit for this IC. [Hint: use the equation substitution method and AND-OR-INVERT funtion given in part (a) for $C _{i+1}$
asked Apr 3, 2019 in Digital Logic ajaysoni1924 194 views
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Using the AND-OR-Invert implementation procedure, show that the output carry in full adder can be expressed as $C _{i+1} = G _i + P _iC _i = (G _i'P _i + G _i'C _i')'$ IC type 74182 is a look-ahead carry generator MSI circuits that generate the carries with AND-OR ... -ahead carries $C _2 C _3 and C _4$ in this IC (HINT: Use the equation substitution method to derive carries in terms of $C _1'$).
asked Apr 3, 2019 in Digital Logic ajaysoni1924 62 views
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The adder-subtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S _2 S _1$ and $C _5$. M A B 0 0111 0110 0 1000 1001 1 0101 1000 1 0000 1010
asked Apr 3, 2019 in Digital Logic ajaysoni1924 476 views
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The adder-subtractor of the figure is used to subtract the following unsigned 4-bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the circuit $?$ what are the binary values of the five outputs of the circuit$?$ Explain How the output is related to the operation of 6 – 9.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 182 views
1 vote
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Construct a BCD-to-Excess-3-code converter with a 4-bit adder.remember that the Excess-3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be done to change the circuit to an excess-3-to-BCD-code converter
asked Apr 3, 2019 in Digital Logic ajaysoni1924 123 views
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Construct a 16-bit parallel adder with four MSI circuits, each containing a four-bit parallel adder. Use a block diagram with 9 inputs and five outputs for each 4-bit adder. Show how the carries are connected between the MSI circuits.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 316 views
3 votes
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Let $S(x,y,z)$ and $C(x,y,z)$ represents the Sum & Carry function of a full adder circuit. Which of the following options best represents $S(x,y,z)$ and $C(x,y,z)$ respectively? $x \oplus y \oplus z, y( x \oplus z)+xy$ $x \oplus y \oplus z, y(x+y+z)$ $x \odot y \odot z, z(x+y)+xy$ $\text{None of these}$
asked Dec 27, 2018 in Digital Logic Ruturaj Mohanty 331 views
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x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d then what will be the maximum Delay of carry look ahead adder circuit? N2 Kd Nkd Nd
asked Nov 12, 2018 in Digital Logic shgarg 329 views
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Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.
asked Nov 7, 2018 in Digital Logic jatin khachane 1 274 views
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$1)$3-bit ripple adder, which adds two 3-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the ... in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?
asked Aug 30, 2018 in Digital Logic srestha 710 views
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A full adder circuit takes 20 ns to generate the carry-out bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec. Usual Solution given The answer ... really calculate the total time taken to perform one round of four bit addition. Right? (Similar old question: https://gateoverflow.in/83500/digitals)
asked Aug 19, 2018 in Digital Logic GateAspirant999 589 views
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How to check whether there is overflow in n-bit parallel adder?
asked Aug 3, 2018 in Digital Logic aditi19 92 views
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A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... doubt is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??
asked May 27, 2018 in Digital Logic BASANT KUMAR 210 views
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One ripple carry adder is adding two n-bit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
asked May 21, 2018 in Digital Logic srestha 213 views
2 votes
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Please elaborate your answer.
asked Jan 9, 2018 in Digital Logic gauravkc 127 views
1 vote
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How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
asked Dec 30, 2017 in Digital Logic AnilGoudar 222 views
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A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.
asked Dec 4, 2017 in Digital Logic shivangi5 191 views
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