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Recent questions tagged adder
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1
Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs ... AND, Or gates. can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?
shikhar500
asked
in
Digital Logic
Sep 14
by
shikhar500
163
views
test-series
digital-logic
adder
1
vote
3
answers
2
NIELIT 2016 MAR Scientist B - Section C: 2
In which of the following adder circuits, the carry look ripple delay is eliminated? Half adder Full adder Parallel adder Carry-look ahead adder
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 31, 2020
by
Lakshman Patel RJIT
2.9k
views
nielit2016mar-scientistb
digital-logic
combinational-circuit
adder
carry-generator
2
votes
3
answers
3
NIELIT 2016 DEC Scientist B (IT) - Section B: 33
How many inputs are required in Full Adder Circuit? $2$ $3$ More than two inputs None of the above
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 31, 2020
by
Lakshman Patel RJIT
680
views
nielit2016dec-scientistb-it
digital-logic
combinational-circuit
adder
0
votes
0
answers
4
Morris Mano Edition 3 Exercise 5 Question 12 (Page No. 199)
It is necessary to design a decimal Adder for two digits represented in Excess-3 code. Show that the correction after adding the two digits with a four-bit binary adder is as follows. The output carry is equal to the carry from ... output carry is 0 then add 1101. construct a four-bit decimal adder using two 4-bit adders and an inverter..
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
663
views
digital-logic
morris-mano
combinational-circuit
adder
0
votes
0
answers
5
Morris Mano Edition 3 Exercise 5 Question 11 (Page No. 198)
Construct a 4-digit BCD adder-subtractor using 4 BCD adders. Use the Block diagram for each component, showing only inputs and outputs.
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
274
views
digital-logic
morris-mano
combinational-circuit
adder
0
votes
1
answer
6
Morris Mano Edition 3 Exercise 5 Question 9 (Page No. 198)
How many Unused Combinations are there in BCD adder?
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
292
views
digital-logic
morris-mano
combinational-circuit
adder
0
votes
0
answers
7
Morris Mano Edition 3 Exercise 5 Question 8 (Page No. 198)
Derive the two-level Boolean expression for the output carry $C _5$ shown in the look-ahead carry generator of the figure
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
353
views
digital-logic
morris-mano
combinational-circuit
adder
1
vote
3
answers
8
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
Assume that the EXCLUSIVE-OR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the four-bit adder of the figure given below?
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
3.6k
views
digital-logic
morris-mano
combinational-circuit
adder
0
votes
0
answers
9
Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
(a) Redefine the carry propagate and carry generate as follows: $P _i = A _i + B _ i$ $G _i = A _iB _i$ ... circuit for this IC. [Hint: use the equation substitution method and AND-OR-INVERT funtion given in part (a) for $C _{i+1}$
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
739
views
digital-logic
morris-mano
combinational-circuit
adder
carry-generator
0
votes
0
answers
10
Morris Mano Edition 3 Exercise 5 Question 5 (Page No. 198)
Using the AND-OR-Invert implementation procedure, show that the output carry in full adder can be expressed as $C _{i+1} = G _i + P _iC _i = (G _i'P _i + G _i'C _i')'$ IC type 74182 is a look-ahead carry generator MSI ... $C _1'$).
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
262
views
digital-logic
morris-mano
combinational-circuit
adder
carry-generator
0
votes
0
answers
11
Morris Mano Edition 3 Exercise 5 Question 4 (Page No. 197)
The adder-subtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S _2 S _1$ and $C _5$. M A B 0 0111 0110 0 1000 1001 1 0101 1000 1 0000 1010
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
2.2k
views
digital-logic
morris-mano
combinational-circuit
adder
digital-circuits
0
votes
0
answers
12
Morris Mano Edition 3 Exercise 5 Question 3 (Page No. 197)
The adder-subtractor of the figure is used to subtract the following unsigned 4-bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the circuit $?$ what are the binary values of the five outputs of the circuit$?$ Explain How the output is related to the operation of 6 – 9.
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
705
views
digital-logic
morris-mano
combinational-circuit
adder
digital-circuits
1
vote
0
answers
13
Morris Mano Edition 3 Exercise 5 Question 2 (Page No. 197)
Construct a BCD-to-Excess-3-code converter with a 4-bit adder.remember that the Excess-3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be done to change the circuit to an excess-3-to-BCD-code converter
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
471
views
digital-logic
morris-mano
combinational-circuit
adder
digital-circuits
7
votes
0
answers
14
Morris Mano Edition 3 Exercise 5 Question 1 (Page No. 197)
Construct a 16-bit parallel adder with four MSI circuits, each containing a four-bit parallel adder. Use a block diagram with 9 inputs and five outputs for each 4-bit adder. Show how the carries are connected between the MSI circuits.
ajaysoni1924
asked
in
Digital Logic
Apr 3, 2019
by
ajaysoni1924
1.2k
views
digital-logic
morris-mano
combinational-circuit
adder
3
votes
1
answer
15
GATE Overflow | Mock GATE | Test 1 | Question: 14
Let $S(x,y,z)$ and $C(x,y,z)$ represents the Sum & Carry function of a full adder circuit. Which of the following options best represents $S(x,y,z)$ and $C(x,y,z)$ respectively? $x \oplus y \oplus z, y( x \oplus z)+xy$ $x \oplus y \oplus z, y(x+y+z)$ $x \odot y \odot z, z(x+y)+xy$ $\text{None of these}$
Ruturaj Mohanty
asked
in
Digital Logic
Dec 27, 2018
by
Ruturaj Mohanty
806
views
go-mockgate-1
digital-logic
adder
digital-circuits
1
vote
3
answers
16
Full adder
Na462
asked
in
Digital Logic
Nov 15, 2018
by
Na462
575
views
digital-logic
carry-generator
adder
full-adder
0
votes
2
answers
17
MadeEasy Workbook: Digital Logic - Adder
x and y are two n bit numbers. these numbers are added by n bit carry look ahead adder which uses k logic levels. if the average gate delay of carry look ahead adder is d then what will be the maximum Delay of carry look ahead adder circuit? N2 Kd Nkd Nd
shgarg
asked
in
Digital Logic
Nov 12, 2018
by
shgarg
1.2k
views
digital-logic
adder
made-easy-test-series
1
vote
0
answers
18
Self Doubt
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.
jatin khachane 1
asked
in
Digital Logic
Nov 7, 2018
by
jatin khachane 1
645
views
digital-logic
adder
1
vote
2
answers
19
Gateforum Test Series: Digital Logic - Adder
Gupta731
asked
in
Digital Logic
Nov 6, 2018
by
Gupta731
364
views
gateforum-test-series
digital-logic
adder
0
votes
2
answers
20
Full adder
Na462
asked
in
Digital Logic
Oct 1, 2018
by
Na462
475
views
digital-logic
adder
carry-generator
2
votes
2
answers
21
Sums on Adder
$1)$3-bit ripple adder, which adds two 3-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, ... both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?
srestha
asked
in
Digital Logic
Aug 30, 2018
by
srestha
2.0k
views
digital-logic
adder
1
vote
1
answer
22
Adder delay
A full adder circuit takes 20 ns to generate the carry-out bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec. Usual Solution given The ... calculate the total time taken to perform one round of four bit addition. Right? (Similar old question: https://gateoverflow.in/83500/digitals)
GateAspirant999
asked
in
Digital Logic
Aug 19, 2018
by
GateAspirant999
3.5k
views
digital-logic
adder
combinational-circuit
digital-circuits
0
votes
0
answers
23
Doubt
How to check whether there is overflow in n-bit parallel adder?
aditi19
asked
in
Digital Logic
Aug 3, 2018
by
aditi19
253
views
adder
0
votes
1
answer
24
gate 2004
A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??
BASANT KUMAR
asked
in
Digital Logic
May 27, 2018
by
BASANT KUMAR
541
views
digital-logic
adder
0
votes
1
answer
25
Adder
One ripple carry adder is adding two n-bit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
srestha
asked
in
Digital Logic
May 21, 2018
by
srestha
885
views
digital-logic
carry-generator
adder
2
votes
0
answers
26
Digital Logic
Please elaborate your answer.
gauravkc
asked
in
Digital Logic
Jan 9, 2018
by
gauravkc
329
views
digital-logic
adder
1
vote
1
answer
27
CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
AnilGoudar
asked
in
Digital Logic
Dec 30, 2017
by
AnilGoudar
406
views
digital-logic
carry-generator
adder
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