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Recent questions tagged adder
0
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1
answer
1
Test series
Consider a $3bit$ number $A$ and $2 bit$ number $B$ are given to a multiplier. The output of multiplier is realized using $AND$ gate and onebit full adders. If the minimum number of $AND$ gates required are $X$ and onebit full adders required are Y, then $X+Y = $ _______
asked
May 31
in
Digital Logic
by
saumya mishra
Junior
(
915
points)

67
views
digitallogic
multiplier
adder
fulladder
0
votes
1
answer
2
gate 2004
A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??
asked
May 27
in
Digital Logic
by
BASANT KUMAR
(
107
points)

26
views
digitallogic
adder
0
votes
1
answer
3
Adder
One ripple carry adder is adding two nbit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
asked
May 21
in
Digital Logic
by
srestha
Veteran
(
86.6k
points)

36
views
digitallogic
carrygenerator
adder
+2
votes
0
answers
4
Digital Logic
Please elaborate your answer.
asked
Jan 9
in
Digital Logic
by
gauravkc
Loyal
(
5.4k
points)

49
views
digitallogic
adder
0
votes
0
answers
5
CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
asked
Dec 30, 2017
in
Digital Logic
by
AnilGoudar
Active
(
4.5k
points)

56
views
digitallogic
carrygenerator
adder
+3
votes
0
answers
6
Modified GATE 2003 question
Consider this GATE 2003 question: https://gateoverflow.in/937/gate200346 Here, instead of XOR gates we had OR gates, then which of the following operations can we perform? $A + B, A  B\ and\ A + 1$
asked
Nov 3, 2017
in
CO & Architecture
by
Rishabh Gupta 2
Boss
(
13.9k
points)

128
views
gate2003
adder
+2
votes
0
answers
7
GATE2003
asked
Oct 22, 2017
in
Digital Logic
by
chetan raghav
(
99
points)

55
views
full
adder
+2
votes
1
answer
8
Digital Systems  Help building a 4 bit Binary adder circuit
asked
Oct 2, 2017
in
Digital Logic
by
Garrett McClure
(
443
points)

255
views
digitallogic
gate
digitalcircuits
adder
halfadder
+1
vote
0
answers
9
made easy book
If the carry propogation delay is 5 in full adder then multiplication of 8 bit number using comultiplier takes(Assume AND gate delay=2)
asked
Sep 17, 2017
in
Digital Logic
by
nikkey123
Active
(
1.5k
points)

57
views
digitallogic
adder
+1
vote
2
answers
10
Which expression is right with respect to carry look header?
asked
Sep 7, 2017
in
Digital Logic
by
hem chandra joshi
Active
(
4.4k
points)

102
views
adder
carrygenerator
0
votes
1
answer
11
adder
This is binary to radix 12 circuit, how?
asked
Aug 31, 2017
in
Digital Logic
by
Sunil8860
(
87
points)

95
views
digitallogic
adder
+5
votes
4
answers
12
ISRO201724
When two $n$bit binary numbers are added the sum will contain at the most $n$ bits $n + 2$ bits $n + 3$ bits $n + 1$ bits
asked
May 7, 2017
in
Digital Logic
by
sh!va
Boss
(
34.1k
points)

3.1k
views
isro2017
digitallogic
adder
+1
vote
1
answer
13
Adder
asked
Jan 4, 2017
in
Digital Logic
by
vaishali jhalani
Loyal
(
5.8k
points)

326
views
digitallogic
adder
0
votes
0
answers
14
Digital: Carry Look Ahead Adder
Que: For Standard 4 bit [Where LSB bit consider at 0th & MSB Consider at 3rd position] carry look ahead adder, what is then fanin of OR gate whose output is C3____? Given Answer: 5 My answer: 4 C3=P2P1P0C0 + P2P1G0 + P2G1 + G2 as Ci+1= PiCi + Gi Please check!
asked
Dec 24, 2016
in
Digital Logic
by
Vijay Thakur
Boss
(
17.1k
points)

227
views
digitallogic
adder
combinational
0
votes
0
answers
15
GATE19884ii
Using binary full adders and other logic gates (if necessary), design an adder for adding 4bit number (including sign) in 2’s complement notation.
asked
Dec 19, 2016
in
Digital Logic
by
jothee
Veteran
(
98.5k
points)

102
views
gate1988
digitallogic
descriptive
adder
0
votes
0
answers
16
full adder
Can anyone explain me this theory with an example(from the third line)...??
asked
Dec 14, 2016
in
Digital Logic
by
Anmol Verma
Active
(
1.4k
points)

73
views
digitallogic
adder
combinational
0
votes
1
answer
17
virtual gate
Which of the following statements is/are true? S1: Carry lookahead adder is faster compared to a ripple carry adder. S2: The cost is higher for a carry lookahead adder compared to a ripple carry adder. (A) S1 only (B) S2 only (C) Both (D) None of these
asked
Dec 8, 2016
in
Digital Logic
by
Tendua
Boss
(
15.7k
points)

161
views
virtualgate
digitallogic
adder
+14
votes
1
answer
18
GATE19901i
Fill in the blanks: In the two bit fulladder/subtractor unit shown in below figure, when the switch is in position 2 ___________ using _________ arithmetic.
asked
Nov 18, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
40k
points)

669
views
gate1990
digitallogic
adder
0
votes
0
answers
19
GATE19873a
Design an $8 \times 8$ multiplier using five 4bits adders and 4 ROM's each programmed to realise $4 \times 4$ multiplier.
asked
Nov 12, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
40k
points)

112
views
gate1987
digitallogic
adder
+1
vote
0
answers
20
Online resource
Can anyone explained me how gate delay is calculated in this link http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=483&cnt=664 According me for 32 bit ripple carry adder, gate delay = (321) Pcarry + Psum Now Pcarry = 1EXOR + 1AND + 1OR = 3 gate delay and Psum = 1EXOR + 1EXOR = 2 gate delay so gate delay = 31*3 + 2 = 95 but given is 65
asked
Oct 20, 2016
in
Digital Logic
by
Digvijaysingh Gautam
Loyal
(
9k
points)

111
views
adder
+1
vote
0
answers
21
Made Easy: Digital Logic: Parallel Adder Delay
asked
Oct 20, 2016
in
Digital Logic
by
Vijay Thakur
Boss
(
17.1k
points)

446
views
digitallogic
combinational
digitalcircuits
adder
madeeasytestseries
+1
vote
1
answer
22
Carry look ahead adder delay
How many gate delays are needed to add for increase of level in multilevel carry look ahead adder? (A) 2 gate delays (B) 3 gate delays (C) 4 gate delays (D) 5 gate delays I really didnt get what it is meant by "to add ... calculating Px and Gx two stages of internal logic for calculating carry one stage calculating final sum So should the answer be 4 gate delays?
asked
Oct 16, 2016
in
Operating System
by
GateAspirant999
Active
(
2.5k
points)

402
views
digitallogic
adder
+8
votes
2
answers
23
Booth vs Add&SHIFT Calculation?
We want to multiply two 32 bit unsigned numbers 70E5F867 * EFB70E1E. . how many add operation is needed in ADDshift and Booth method? Any idea how I can solve this? the solution give a 20 and 6.
asked
Jul 28, 2016
in
CO & Architecture
by
Sara Nimlon
(
159
points)

679
views
coandarchitecture
boothsalgorithm
adder
+2
votes
2
answers
24
UGCNETDec2013II40
Which of the following statements are true? A circuit that adds two bits, producing a sum bit and carry bit is called half adder A circuit that adds two bits, producing a sum bit and carry bit is called full adder A circuit that adds two bits and a carry bit ... as input and produces its complement is called an inverter I & II II & III I, II, III I, III & IV
asked
Jul 26, 2016
in
Digital Logic
by
jothee
Veteran
(
98.5k
points)

249
views
ugcnetdec2013ii
digitallogic
adder
+6
votes
2
answers
25
ISRO200703
The circuit shown in the given figure is a full adder full subtracter shift register decade counter
asked
Jun 5, 2016
in
Digital Logic
by
jothee
Veteran
(
98.5k
points)

1.8k
views
isro2007
digitallogic
digitalcircuits
adder
+1
vote
0
answers
26
ISI2012CS2b
The CPU of a computer has a ripplecarry implementation of a 2's complement adder that takes two 8bit integers $A = a_7a_6 \dots a_0$ and $B = b_7b_6 \dots b_0$ as inputs, and produces a sum $S = s_7s_6 \dots s_0$, where $a_i, b_i, c_i \in \{0, 1\} \ ... = 1001 1001 and $B$ = 1000 0110. What will be the output $S$ of the adder? How will the value of $S$ be interpreted by the machine?
asked
Jun 2, 2016
in
Digital Logic
by
jothee
Veteran
(
98.5k
points)

75
views
descriptive
isi2012
digitallogic
adder
+29
votes
5
answers
27
GATE2016133
Consider a carry look ahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is $\Theta (1)$ $\Theta (\log(n))$ $\Theta (\sqrt{n})$ $\Theta (n)$)
asked
Feb 12, 2016
in
Digital Logic
by
Sandeep Singh
Loyal
(
7.8k
points)

5.6k
views
gate20161
digitallogic
adder
normal
+25
votes
3
answers
28
GATE2016207
Consider an eightbit ripplecarry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________
asked
Feb 12, 2016
in
Digital Logic
by
Akash Kanase
Boss
(
42.5k
points)

3.9k
views
gate20162
digitallogic
adder
normal
numericalanswers
0
votes
1
answer
29
Number of AND gates for carry lookahead generator
asked
Jan 15, 2016
in
Digital Logic
by
shikharV
Active
(
4.1k
points)

1.1k
views
digitallogic
adder
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