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Recent questions tagged adder
0
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0
answers
1
Nielit STA 2018
Minimum number of Full adders and half adders required by the BCD adder to add two decimal digits.
asked
Dec 5, 2018
in
Digital Logic
by
Robert Soram
(
41
points)

38
views
digitallogic
adder
0
votes
1
answer
2
Full adder
asked
Nov 15, 2018
in
Digital Logic
by
Na462
Loyal
(
7.9k
points)

52
views
digitallogic
carrygenerator
adder
fulladder
0
votes
0
answers
3
Self Doubt
Suppose we are using 4bit carry lookahead adder modules to build a 64 bit adder with twolevel carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worstcase delay of the 64bit adder will be ……….. nanoseconds.
asked
Nov 7, 2018
in
Digital Logic
by
jatin khachane 1
Loyal
(
5.4k
points)

56
views
digitallogic
adder
0
votes
1
answer
4
Full adder
asked
Oct 1, 2018
in
Digital Logic
by
Na462
Loyal
(
7.9k
points)

58
views
digitallogic
adder
carrygenerator
0
votes
1
answer
5
Sums on Adder
$1)$3bit ripple adder, which adds two 3bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, ... both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder?
asked
Aug 30, 2018
in
Digital Logic
by
srestha
Veteran
(
106k
points)

154
views
digitallogic
adder
0
votes
1
answer
6
Adder delay
A full adder circuit takes 20 ns to generate the carryout bit and 40 ns for the sum bit. When 4, 1 bit full adders are cascaded, the maximum rate of additions per second will be $\text{____} \times 10^6 $sec. Usual Solution given The ... calculate the total time taken to perform one round of four bit addition. Right? (Similar old question: https://gateoverflow.in/83500/digitals)
asked
Aug 19, 2018
in
Digital Logic
by
GateAspirant999
Active
(
2.8k
points)

111
views
digitallogic
adder
combinational
digitalcircuits
0
votes
0
answers
7
Doubt
How to check whether there is overflow in nbit parallel adder?
asked
Aug 3, 2018
in
Digital Logic
by
aditi19
Active
(
2.2k
points)

40
views
adder
0
votes
0
answers
8
doubt
How to Calculate Propagation Delay In Carry Look Ahead Adder.
asked
Jul 18, 2018
in
Digital Logic
by
bhavnakumrawat5
(
193
points)

31
views
carry
look
ahead
adder
0
votes
0
answers
9
Minimum number of nand or nor gates for 2 bit adder.
What are the minimum number of nand or nor gates required for 2 bit adder ( ie. 4 input A,B,C,D) ?
asked
Jul 3, 2018
in
Digital Logic
by
adil.wadood
(
7
points)

181
views
digitallogic
adder
combinational
nand
nor
0
votes
1
answer
10
Test series
Consider a $3bit$ number $A$ and $2 bit$ number $B$ are given to a multiplier. The output of multiplier is realized using $AND$ gate and onebit full adders. If the minimum number of $AND$ gates required are $X$ and onebit full adders required are Y, then $X+Y = $ _______
asked
May 31, 2018
in
Digital Logic
by
saumya mishra
Active
(
1.5k
points)

168
views
digitallogic
multiplier
adder
fulladder
0
votes
1
answer
11
gate 2004
A $4 \hspace{0.1cm} bit$ carry lookahead adder which add two $4$ $bit$ number is designed using $AND ,OR,NOT,NAND,NOR$ gates only.Assuming that all the inputs are available in both complemented and uncomplemented form and the delay of each gate is one time ... is if we take same $4$ $bit$ number instead of lookahead adder if we take parallel adder what will be overall propagation delay??
asked
May 27, 2018
in
Digital Logic
by
BASANT KUMAR
Active
(
2.3k
points)

99
views
digitallogic
adder
0
votes
1
answer
12
Adder
One ripple carry adder is adding two nbit integers. The time complexity to perform addition using this adder is (We know carry look ahead adder takes time log n. Is it similar for other adders too). Plz also share some good resource about these two adders
asked
May 21, 2018
in
Digital Logic
by
srestha
Veteran
(
106k
points)

68
views
digitallogic
carrygenerator
adder
+2
votes
0
answers
13
Digital Logic
Please elaborate your answer.
asked
Jan 9, 2018
in
Digital Logic
by
gauravkc
Loyal
(
7.2k
points)

59
views
digitallogic
adder
+1
vote
0
answers
14
CLA and RCA delays.
How to analyse the delays of Ripple carry adder and Carry look ahead adder. Please explain with Example.
asked
Dec 30, 2017
in
Digital Logic
by
AnilGoudar
Active
(
4.7k
points)

93
views
digitallogic
carrygenerator
adder
+3
votes
0
answers
15
Modified GATE 2003 question
Consider this GATE 2003 question: https://gateoverflow.in/937/gate200346 Here, instead of XOR gates we had OR gates, then which of the following operations can we perform? $A + B, A  B\ and\ A + 1$
asked
Nov 3, 2017
in
CO & Architecture
by
Rishabh Gupta 2
Boss
(
15.9k
points)

170
views
gate2003
adder
+2
votes
0
answers
16
GATE2003
asked
Oct 22, 2017
in
Digital Logic
by
chetan raghav
(
107
points)

69
views
full
adder
+2
votes
1
answer
17
Digital Systems  Help building a 4 bit Binary adder circuit
asked
Oct 2, 2017
in
Digital Logic
by
Garrett McClure
(
443
points)

325
views
digitallogic
gate
digitalcircuits
adder
halfadder
+1
vote
0
answers
18
made easy book
If the carry propogation delay is 5 in full adder then multiplication of 8 bit number using comultiplier takes(Assume AND gate delay=2)
asked
Sep 17, 2017
in
Digital Logic
by
nikkey123
Active
(
1.5k
points)

75
views
digitallogic
adder
+1
vote
2
answers
19
Which expression is right with respect to carry look header?
(i) Ci +1= Gi+ PiCi (ii) Ci +1= G(i+1) + P(i+1)Ci https://www.youtube.com/watch?v=9lyqSVKbyz8&index=116&list=PLBlnK6fEyqRjMH3mWf6kwqiTbT798eAOm i or ii ?
asked
Sep 7, 2017
in
Digital Logic
by
hem chandra joshi
Active
(
4.7k
points)

113
views
adder
carrygenerator
0
votes
1
answer
20
adder
This is binary to radix 12 circuit, how?
asked
Aug 31, 2017
in
Digital Logic
by
Sunil8860
(
141
points)

143
views
digitallogic
adder
+5
votes
4
answers
21
ISRO201724
When two $n$bit binary numbers are added the sum will contain at the most $n$ bits $n + 2$ bits $n + 3$ bits $n + 1$ bits
asked
May 7, 2017
in
Digital Logic
by
sh!va
Boss
(
35.1k
points)

3.3k
views
isro2017
digitallogic
adder
+1
vote
1
answer
22
Adder
asked
Jan 4, 2017
in
Digital Logic
by
vaishali jhalani
Loyal
(
6k
points)

341
views
digitallogic
adder
0
votes
1
answer
23
Digital: Carry Look Ahead Adder
Que: For Standard 4 bit [Where LSB bit consider at 0th & MSB Consider at 3rd position] carry look ahead adder, what is then fanin of OR gate whose output is C3____? Given Answer: 5 My answer: 4 C3=P2P1P0C0 + P2P1G0 + P2G1 + G2 as Ci+1= PiCi + Gi Please check!
asked
Dec 24, 2016
in
Digital Logic
by
Vijay Thakur
Boss
(
17.2k
points)

278
views
digitallogic
adder
combinational
0
votes
0
answers
24
GATE19884ii
Using binary full adders and other logic gates (if necessary), design an adder for adding 4bit number (including sign) in 2’s complement notation.
asked
Dec 19, 2016
in
Digital Logic
by
jothee
Veteran
(
112k
points)

136
views
gate1988
digitallogic
descriptive
adder
0
votes
0
answers
25
full adder
Can anyone explain me this theory with an example(from the third line)...??
asked
Dec 14, 2016
in
Digital Logic
by
Anmol Verma
Active
(
1.6k
points)

78
views
digitallogic
adder
combinational
0
votes
1
answer
26
virtual gate
Which of the following statements is/are true? S1: Carry lookahead adder is faster compared to a ripple carry adder. S2: The cost is higher for a carry lookahead adder compared to a ripple carry adder. (A) S1 only (B) S2 only (C) Both (D) None of these
asked
Dec 8, 2016
in
Digital Logic
by
Tendua
Boss
(
16.1k
points)

172
views
virtualgate
digitallogic
adder
+18
votes
1
answer
27
GATE19901i
Fill in the blanks: In the two bit fulladder/subtractor unit shown in below figure, when the switch is in position $2$ ___________ using _________ arithmetic.
asked
Nov 18, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
40.8k
points)

1.2k
views
gate1990
digitallogic
adder
0
votes
0
answers
28
GATE19873a
Design an $8 \times 8$ multiplier using five 4bits adders and 4 ROM's each programmed to realise $4 \times 4$ multiplier.
asked
Nov 12, 2016
in
Digital Logic
by
makhdoom ghaya
Boss
(
40.8k
points)

136
views
gate1987
digitallogic
adder
+1
vote
0
answers
29
Online resource
Can anyone explained me how gate delay is calculated in this link http://iitkgp.vlab.co.in/?sub=38&brch=120&sim=483&cnt=664 According me for 32 bit ripple carry adder, gate delay = (321) Pcarry + Psum Now Pcarry = 1EXOR + 1AND + 1OR = 3 gate delay and Psum = 1EXOR + 1EXOR = 2 gate delay so gate delay = 31*3 + 2 = 95 but given is 65
asked
Oct 20, 2016
in
Digital Logic
by
Digvijaysingh Gautam
Loyal
(
9.1k
points)

126
views
adder
+1
vote
1
answer
30
Made Easy: Digital Logic: Parallel Adder Delay
There is a general approach to sove such question, i.e Carry Propagation Delay*(n1) + 1 sum propagation delay. therefore answer should be 3*4.8 + 4.8 = 14.4+4.8 = 19.2 should be the answer. Second Approach: there are 3 levels in ... comes to 12 micro secs. Which one is correct approach? if i remember it is a gate question and answer is 19.2 micro sec
asked
Oct 20, 2016
in
Digital Logic
by
Vijay Thakur
Boss
(
17.2k
points)

629
views
digitallogic
combinational
digitalcircuits
adder
madeeasytestseries
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