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Recent questions tagged digitalcounter
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UGCNETJune2019II15
What will be the number of states when a MOD$2$ counter is followed by a MOD$5$ counter? $5$ $10$ $15$ $20$
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Jul 2
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Digital Logic
by
Arjun
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2
Morris Mano Edition 3 Exercise 7 Question 32 (Page No. 305)
Construct a Johnson counter for ten timing signals.
asked
Apr 6
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Digital Logic
by
ajaysoni1924
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Morris Mano Edition 3 Exercise 7 Question 31 (Page No. 305)
Complete the design of Johnson counter of the figure showing the output of the eight timing signals using eight AND gates.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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Morris Mano Edition 3 Exercise 7 Question 27 (Page No. 305)
Using two circuits of the type shown in the figure, construct a binary counter that counts from 0 through binary 64.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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5
Morris Mano Edition 3 Exercise 7 Question 26 (Page No. 305)
Construct a mod 12 counter using the circuit specified in the figure.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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6
Morris Mano Edition 3 Exercise 7 Question 25 (Page No. 305)
Construct a BCD counter using the circuit specified in the figure and a AND gate.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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10.5k
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9
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7
Morris Mano Edition 3 Exercise 7 Question 24 (Page No. 305)
Show the connection between four IC binary counters with the parallel load to produce a 16bit binary counter with the parallel load. Use a block diagram for each IC.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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Morris Mano Edition 3 Exercise 7 Question 23 (Page No. 304)
Design a synchronous BCD counter with JK flipflops
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Apr 6
in
Digital Logic
by
ajaysoni1924
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9
Morris Mano Edition 3 Exercise 7 Question 22 (Page No. 304)
verify the flipflop input functions of the synchronous BCD counter specified in the table given below. Draw the logic diagram of the BCD counter and include a count enable control input.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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10
Morris Mano Edition 3 Exercise 7 Question 21 (Page No. 304)
Modify the counter given in the figure so that when both the up and down control inputs are equal to 1. the counter does not change state, but remains in the same count.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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11
Morris Mano Edition 3 Exercise 7 Question 20 (Page No. 304)
Design a 4bit binary synchronous counter with D flipflops.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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12
Morris Mano Edition 3 Exercise 7 Question 19 (Page No. 304)
Design a 4bit ripple counter with D flipflops.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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13
Morris Mano Edition 3 Exercise 7 Question 18 (Page No. 304)
Determine the next state for each of the six unused states in the BCD ripple counter shown in the figure. Determine whether it is selfcorrecting.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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14
Morris Mano Edition 3 Exercise 7 Question 17 (Page No. 304)
How many flipflops will be complemented in a 10bit binary ripple counter to reach the next count after the following count? 1001100111; 0011111111;
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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15
Morris Mano Edition 3 Exercise 7 Question 16 (Page No. 304)
A flipflop has 10 nanosecond delay from the time its CP input goes from 1 to 0 to the time the output is complemented. What is the maximum delay in the 10bit binary ripple counter that uses these flipflop? What is the maximum frequency the counter can operate reliably.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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16
Morris Mano Edition 3 Exercise 7 Question 15 (Page No. 304)
Construct a BCD ripple counter using a 4bit binary ripple counter that can be cleared asynchronously and an external NAND gate.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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17
Morris Mano Edition 3 Exercise 7 Question 14 (Page No. 304)
Draw the logic diagram of a 4bit binary ripple down counter using the following. Flipflops that trigger on the positive edge transition of the clock. Flipflop that trigger on the negative edge transition of the clock.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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24
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18
Morris Mano Edition 3 Exercise 7 Question 13 (Page No. 304)
Draw the logic diagram of a 4bit binary ripple counter using flipflops that trigger on the positiveedge transition.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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10.5k
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digitallogic
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19
Morris Mano Edition 3 Exercise 6 Question 25 (Page No. 255)
Design the following nonbinary sequence counter as specified in each case. Treat the unused states as don't cares conditions. Analyze the final circuit to ensure that it is selfcorrecting. If your design produces a nonselfcorrecting ... . Design a counter with the following repeated binary sequence 0,1,3, 7,6,4. Use T flipflops.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
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20
Ace academy workbook
Till what value of mod counter you will call it? As per my understanding the maximum number it is counting is 5 so I call it as mod 6 counter but in in the workbook it is given as mod 5 counter and their explanation is that number of states are 5 that's why it is a mod 5 counter. What is correct and why? please help me.
asked
Jan 27
in
Digital Logic
by
Shashankesh Upadhyay
(
43
points)

151
views
digitallogic
digitallogic
digitalcounter
0
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0
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21
MadeEasy Subject Test 2019: Digital Logic  Digital Counter
Consider the circuit given below. Assume initially flipflops are in reset state. What will be the mod of above digital circuit?
asked
Jan 27
in
Digital Logic
by
snaily16
(
245
points)

90
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digitallogic
digitalcounter
madeeasytestseries2019
madeeasytestseries
0
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0
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22
Asynchronous counter (Applied course mock 3)
MOD8 synchronous down counter MOD8 asynchronous up counter MOD10 asynchronous up counter MOD8 asynchronous down counter Please explain why it is down counter?
asked
Jan 15
in
Digital Logic
by
Mk Utkarsh
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35.7k
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117
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digitalcounter
0
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0
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23
MadeEasy Subject Test 2019: Digital Logic  Digital Counter
Initially all flipsflops in the circuit are cleared to zero , what is the mod value of the counter ___________ I got – > 3 sorry for the poor image quality
asked
Jan 14
in
Digital Logic
by
Magma
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(
13.8k
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128
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digitallogic
digitalcounter
madeeasytestseries
madeeasytestseries2019
0
votes
0
answers
24
MadeEasy Test Series: Digital Logic  Digital Counter
asked
Jan 11
in
Digital Logic
by
jatin khachane 1
Loyal
(
7.3k
points)

164
views
madeeasytestseries
digitallogic
flipflop
digitalcounter
0
votes
0
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25
MadeEasy Test Series: Digital Logic  Digital Counter
An AB flipflop (FF) is constructed from a JKFF as shown in the figure. The expression for the next state J=AB’+BA’ and K=A+B characteristic equation of JK FF Qn+1=JQn’+KQn
asked
Jan 6
in
Digital Logic
by
Shivam Kasat
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(
3.2k
points)

55
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madeeasytestseries
digitallogic
digitalcounter
0
votes
0
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26
self doubt
In a Johnson’s counter LSB is complemented and a circular right shift operation has to be done to get the next state. For ring counter also a shortcut exists ?
asked
Jan 4
in
Digital Logic
by
amitqy
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(
1.8k
points)

36
views
digitalcounter
digitallogic
0
votes
0
answers
27
Self Doubt on Counters
If in question it is given to find no. of counting states of a counter, does it mean that we need to find Mod of the counter or just the no. of distinct states that the counter can have?
asked
Jan 2
in
Digital Logic
by
Subham Nagar
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(
1k
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37
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digitalcounter
flipflop
0
votes
1
answer
28
MadeEasy Workbook: Digital Logic  Digital Counter
How to solve this?
asked
Jan 1
in
Digital Logic
by
Jyoti Kumari97
(
181
points)

97
views
digitallogic
digitalcounter
madeeasybooklet
0
votes
0
answers
29
Preset Counters
A 4bit Preset table UP counter has preset input 0111. the preset operation takes place as soon as the counter becomes maximum i.e. 1111. The modulus of the counter is? my answer is 16 but correct ans is 8 . doesn’t it mean whenever input is 1111 counter will again start from 0000 and goes on till 1111? how this preset counter works, explain pls?
asked
Dec 13, 2018
in
Digital Logic
by
Ashwani Yadav
Active
(
1.2k
points)

88
views
digitalcounter
0
votes
0
answers
30
Gateforum Test Series: Digital Logic  Digital Counter
The MOD value (or) number of states in the ripple counter as shown in the figure is? Answer given: Mod 7 counter. My doubt is that won't it go till 111 and then the counter is cleared as the input to NAND gate is taken from the output of the flipflops?
asked
Dec 11, 2018
in
Digital Logic
by
Parth Shah
Junior
(
709
points)

31
views
gateforumtestseries
digitallogic
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