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Recent questions tagged digital-counter

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ripple counter
In a 4-bit binary ripple counter, for every input clock pulse (a) All the flip-flops get clocked simultaneously. (b) Only one flip-flop get clocked at a time. (c) Two of the flip-flops get clocked at a time. (d) All the above statements are false.

someshawasthi asked in Digital Logic Jan 18

by someshawasthi

103 views

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2

self doubt
if i have given 2 flip flop clock simultaneously and 2 flip flop clock non simultaneously what is it synchronous counter or asynchronous counter ? why?

someshawasthi asked in Digital Logic Jan 18

by someshawasthi

73 views

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1 answer

3

Made Easy Test Series Question
The frequency of the pulse at D is __________ Hz.

prnv28 asked in Digital Logic Dec 31, 2021

by prnv28

552 views

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4

Made Easy Test Series Question
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.

prnv28 asked in Digital Logic Dec 31, 2021

by prnv28

963 views

9 votes

3 answers

5

GATE CSE 2021 Set 1 | Question: 28
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$

Arjun asked in Digital Logic Feb 18, 2021

by Arjun

4.6k views

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4 answers

6

NIELIT 2017 OCT Scientific Assistant A (IT) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns

Lakshman Bhaiya asked in Digital Logic Aug 28, 2020

by Lakshman Bhaiya

679 views

1 vote

2 answers

7

NIELIT 2017 OCT Scientific Assistant A (CS) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns

Lakshman Bhaiya asked in Digital Logic Aug 28, 2020

by Lakshman Bhaiya

672 views

5 votes

1 answer

8

UGC NET CSE | June 2019 | Part 2 | Question: 15
What will be the number of states when a MOD-$2$ counter is followed by a MOD-$5$ counter? $5$ $10$ $15$ $20$

Arjun asked in Digital Logic Jul 2, 2019

by Arjun

1.3k views

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9

Morris Mano Edition 3 Exercise 7 Question 32 (Page No. 305)
Construct a Johnson counter for ten timing signals.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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10

Morris Mano Edition 3 Exercise 7 Question 31 (Page No. 305)
Complete the design of Johnson counter of the figure showing the output of the eight timing signals using eight AND gates.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

446 views

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11

Morris Mano Edition 3 Exercise 7 Question 27 (Page No. 305)
Using two circuits of the type shown in the figure, construct a binary counter that counts from 0 through binary 64.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

170 views

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12

Morris Mano Edition 3 Exercise 7 Question 26 (Page No. 305)
Construct a mod -12 counter using the circuit specified in the figure.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

239 views

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Recent questions tagged digital-counter