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Recent questions tagged digitalcounter
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1
Preset Counters
A 4bit Preset table UP counter has preset input 0111. the preset operation takes place as soon as the counter becomes maximum i.e. 1111. The modulus of the counter is? my answer is 16 but correct ans is 8 . doesn’t it mean whenever input is 1111 counter will again start from 0000 and goes on till 1111? how this preset counter works, explain pls?
asked
3 days
ago
in
Digital Logic
by
Ashwani Yadav
(
421
points)

7
views
digitalcounter
0
votes
0
answers
2
#TarGATE
The MOD value (or) number of states in the ripple counter as shown in the figure is? Answer given: Mod 7 counter. My doubt is that won't it go till 111 and then the counter is cleared as the input to NAND gate is taken from the output of the flipflops?
asked
5 days
ago
in
Digital Logic
by
Parth Shah
(
363
points)

13
views
gateforumtestseries
digitallogic
digitalcounter
0
votes
0
answers
3
#TarGATE
The circuit shown in figure is using one 4bit BCD counter and one 4bit binary counter. The MOD value for the counter is ?
asked
5 days
ago
in
Digital Logic
by
Parth Shah
(
363
points)

17
views
gateforumtestseries
digitallogic
digitalcounter
0
votes
0
answers
4
GATEECE2017
answer is D but I'm getting A. pls tell where am I going wrong?
asked
Nov 20
in
Digital Logic
by
aditi19
Active
(
2.1k
points)

63
views
digitallogic
sequentialcircuit
flipflop
digitalcounter
finiteautomata
+1
vote
1
answer
5
Self doubt
No of JK / T FFs needed to design synchronous counter for sequence 1,4,2,3,1,4,2,3,1,4...
asked
Nov 9
in
Digital Logic
by
jatin khachane 1
Active
(
3.3k
points)

51
views
digitallogic
digitalcounter
0
votes
0
answers
6
Sequential Circuits  Counters
A mod2 counter followed by a mod5 counter is a) Same as mod5 counter followed by mod2 counter b) A decade counter c) A mod7 counter d) None
asked
Nov 3
in
Digital Logic
by
garvit_vijai
(
149
points)

50
views
digitalcircuits
sequentialcircuit
digitalcounter
0
votes
0
answers
7
synchronous counters
What will be the output frequency of a 10 bit ring counter if the input frequency is 1500k Hz. Kindly explain using diagram.
asked
Oct 22
in
Digital Logic
by
Kaushal Sanadhya
(
63
points)

25
views
digitalcounter
0
votes
2
answers
8
Synchronous Counter Circuit
In the given synchronous Counter circuit, initially all Outputs are Reset. It is required to replace FF2 with AB Flip Flop. The FF2 inputs would be: A. A = Q1 and B = Q1' B. A = Q1' and B = Q1' C. A = Q1.Q0 and B = Q1.Q0 D. A = Qo' and B = Qo'
asked
Oct 10
in
Digital Logic
by
Na462
Loyal
(
7.5k
points)

42
views
digitallogic
synchronousasynchronouscircuits
digitalcounter
0
votes
0
answers
9
virtualgate
asked
Oct 9
in
Digital Logic
by
Dharmendra Lodhi
Active
(
2.8k
points)

47
views
virtualgate
digitalcounter
0
votes
1
answer
10
Digital electronics
asked
Oct 6
in
Digital Logic
by
pilaniya
(
7
points)

27
views
digitalcounter
0
votes
0
answers
11
Synchronous Counter
asked
Oct 1
in
Digital Logic
by
Na462
Loyal
(
7.5k
points)

29
views
digitallogic
synchronousasynchronouscircuits
digitalcounter
0
votes
1
answer
12
Counter
A MOD2 ripple counter is cascaded with a MOD8 synchronous counter. The resulting circuit will form a counter of MOD = ___________. ____________________________________________________________________ my problem is how can a asynchronous counter work like an synchronous counter? diagram required with explanation for clearity
asked
Aug 26
in
Digital Logic
by
srestha
Veteran
(
104k
points)

88
views
digitallogic
digitalcounter
+1
vote
0
answers
13
Johnson Counter Doubt
I have found this statement about Johnson Counter : A Johnson counter requires decoding gates whereas a ring counter doesn't. As with the binary counter, one logic gate (AND gate) is required to decode each state, but with the Johnson counter, each ... to implement it? The reference link is here: https://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#johnson
asked
Jul 27
in
Digital Logic
by
dan31
(
287
points)

23
views
digitallogic
digitalcounter
0
votes
1
answer
14
UGC NET July 2018 Q 94
asked
Jul 10
in
Digital Logic
by
Sanjay Sharma
Veteran
(
50k
points)

195
views
sequentialcircuit
digitalcounter
0
votes
1
answer
15
Asynchronous counter
according to me the answer should be 6 but is 7 pls explain
asked
Jun 19
in
Digital Logic
by
Tarun322
(
31
points)

81
views
digitalcounter
asynchronouscounter
upcounter
0
votes
1
answer
16
Counter
Answer given is 4 but mine is 2
asked
May 22
in
Digital Logic
by
ajaysoni1924
(
155
points)

54
views
digitallogic
digitalcounter
flipflop
0
votes
1
answer
17
Counters
I didn't understand the concept of Counters well Can anybody provide any online Source or Explain the Concept of Counter which includes Johnson Counter and what is meant by mod 3,mod 6 etc Counters ?
asked
Apr 17
in
Digital Logic
by
Na462
Loyal
(
7.5k
points)

74
views
digitalcounter
0
votes
0
answers
18
GFG question 2018
Consider following counters: Counter1: Counter2: Which of the following option is correct? (A) Counter1 is a threebit counter which counts 0, 1, 2, 4, 5, 7, 0, . and Counter2 is a threebit counter which counts 0, 3, 6, 1, 4, 7, 2, 5, 0, 3, . (B) Counter1 is a ... 6, 1, 4, 7, 2, 5, 0, 3, . and Counter2 is a threebit counter which counts 0, 1, 2, 3, 5, 6, 0, .
asked
Feb 1
in
Digital Logic
by
Utsav09
Active
(
1.2k
points)

103
views
digitallogic
digitalcounter
+2
votes
1
answer
19
Digital01
MOD Value ? FF clears at $Q_{3}Q_{2}Q_{1}$ = 110 So mod value is 6 ...??
asked
Jan 17
in
Digital Logic
by
Anjan
Active
(
1.7k
points)

111
views
digitallogic
digitalcounter
0
votes
0
answers
20
self doubt
does synchronous counters act as frequency dividers? if input frequency to a 5 bit johnson counter is 500 hz what is the output frequency ?
asked
Jan 15
in
Digital Logic
by
Venkat Sai
Active
(
3.5k
points)

51
views
digitallogic
digitalcounter
+2
votes
0
answers
21
Counter
Find the Mod Value for the counter My ans is MOD5 counter but given is MOD3 please explain ....
asked
Jan 11
in
Digital Logic
by
Anjan
Active
(
1.7k
points)

129
views
digitallogic
digitalcounter
0
votes
0
answers
22
Time Calculation in counters
Describe the steps with plausible assertions.
asked
Dec 24, 2017
in
Digital Logic
by
ashwina
Active
(
2.1k
points)

51
views
digitalcounter
0
votes
0
answers
23
Digital Logic: Counters
Consider the following question: My explanation: A clock cycle time should be large enough that all flipflops can come in a stable state before the next clock cycle starts. Suppose cycle 1 is just completed and cycle 2 is just about to start: 1. to ... on the following link, it is $\frac{1}{20ns}$. Can someone explain, please? https://gateoverflow.in/26442/gate1991_5c
asked
Dec 18, 2017
in
Digital Logic
by
Manu Thakur
Boss
(
41.5k
points)

99
views
digitalcounter
digitalcircuits
flipflop
0
votes
1
answer
24
MADE EASY test series DIGITAL LOGIC  Synchronous counters
asked
Dec 14, 2017
in
Digital Logic
by
vishnu priyan
(
413
points)

218
views
digitalcircuits
madeeasytestseries
flipflop
sequential
digitalcounter
0
votes
2
answers
25
Output clock frequency
asked
Dec 6, 2017
in
Digital Logic
by
Parshu gate
Active
(
5k
points)

250
views
digitallogic
clockfrequency
digitalcounter
0
votes
0
answers
26
Counters
Is this statement true? Nonbinary counter means synchronous counter?
asked
Dec 3, 2017
in
Digital Logic
by
sunaina rawat
(
223
points)

41
views
digitalcounter
digitalcircuits
digitallogic
sequential
0
votes
1
answer
27
Ripple carry counter
For a Nstage ripple carry counter which uses flipflops of propagation delay = P ns and clock period of C ns. Give the expression of the frequency of input signal?
asked
Nov 17, 2017
in
Digital Logic
by
Tuhin Dutta
Loyal
(
8.5k
points)

180
views
digitallogic
digitalcounter
+1
vote
0
answers
28
counters
If a full modulus counter having 10 flipflops is initially at 0. After how many pulses it will count 0000001100 ? (A) 2060 (B) 1036 (C) 3048 (D) ALL
asked
Nov 12, 2017
in
Digital Logic
by
Parshu gate
Active
(
5k
points)

142
views
digitalcounter
flipflop
+1
vote
1
answer
29
counters
mod 1 mod 3 mod 4 mod 2
asked
Nov 10, 2017
in
Digital Logic
by
Parshu gate
Active
(
5k
points)

66
views
digitalcounter
flipflop
digitalcircuits
0
votes
1
answer
30
Flip flops
Consider the complemented circuit shown below: If the initial value of the output Q1 Q0 is 00, then the next three values of Q1 Q0 are: 10,01,01,00 10,01,11,00 10,01,00,01 10,01,10,00 Doubt: I am getting a sequence which is not matching with any of the option
asked
Nov 8, 2017
in
Digital Logic
by
akb1115
Active
(
3.3k
points)

205
views
digitallogic
flipflop
digitalcircuits
digitalcounter
sequential
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