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Recent questions tagged digitalcounter
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1
Ace academy workbook
Till what value of mod counter you will call it? As per my understanding the maximum number it is counting is 5 so I call it as mod 6 counter but in in the workbook it is given as mod 5 counter and their explanation is that number of states are 5 that's why it is a mod 5 counter. What is correct and why? please help me.
asked
Jan 27
in
Digital Logic
by
Shashankesh Upadhyay
(
61
points)

47
views
digitallogic
digitallogic
digitalcounter
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votes
0
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2
Asynchronous counter (Applied course mock 3)
MOD8 synchronous down counter MOD8 asynchronous up counter MOD10 asynchronous up counter MOD8 asynchronous down counter Please explain why it is down counter?
asked
Jan 15
in
Digital Logic
by
Mk Utkarsh
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34.1k
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95
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digitalcounter
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0
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3
self doubt
In a Johnson’s counter LSB is complemented and a circular right shift operation has to be done to get the next state. For ring counter also a shortcut exists ?
asked
Jan 4
in
Digital Logic
by
amitqy
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1.4k
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31
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digitalcounter
digitallogic
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4
Self Doubt on Counters
If in question it is given to find no. of counting states of a counter, does it mean that we need to find Mod of the counter or just the no. of distinct states that the counter can have?
asked
Jan 2
in
Digital Logic
by
Subham Nagar
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1.1k
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28
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digitalcounter
flipflop
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votes
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answers
5
Counters made easy self doubt
asked
Dec 23, 2018
in
Digital Logic
by
Na462
Loyal
(
8.6k
points)

75
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digitalcounter
madeeasytestseries
flipflop
sequential
digitalcircuits
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6
ME Test Series
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is turned for 80 seconds. The traffic has to be implemented using FSM. The only input to this FSM is a clock of 10 second period. The minimum number of flipflops required to implement this FSM is?
asked
Dec 22, 2018
in
Digital Logic
by
Parth Shah
Junior
(
593
points)

106
views
madeeasytestseries
digitallogic
digitalcounter
0
votes
0
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7
Preset Counters
A 4bit Preset table UP counter has preset input 0111. the preset operation takes place as soon as the counter becomes maximum i.e. 1111. The modulus of the counter is? my answer is 16 but correct ans is 8 . doesn’t it mean whenever input is 1111 counter will again start from 0000 and goes on till 1111? how this preset counter works, explain pls?
asked
Dec 13, 2018
in
Digital Logic
by
Ashwani Yadav
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1.1k
points)

57
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digitalcounter
0
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0
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8
#TarGATE
The MOD value (or) number of states in the ripple counter as shown in the figure is? Answer given: Mod 7 counter. My doubt is that won't it go till 111 and then the counter is cleared as the input to NAND gate is taken from the output of the flipflops?
asked
Dec 11, 2018
in
Digital Logic
by
Parth Shah
Junior
(
593
points)

21
views
gateforumtestseries
digitallogic
digitalcounter
0
votes
0
answers
9
#TarGATE
The circuit shown in figure is using one 4bit BCD counter and one 4bit binary counter. The MOD value for the counter is ?
asked
Dec 11, 2018
in
Digital Logic
by
Parth Shah
Junior
(
593
points)

34
views
gateforumtestseries
digitallogic
digitalcounter
0
votes
2
answers
10
GATEECE2017
answer is D but I'm getting A. pls tell where am I going wrong?
asked
Nov 20, 2018
in
Digital Logic
by
aditi19
Active
(
2.3k
points)

87
views
digitallogic
sequentialcircuit
flipflop
digitalcounter
finiteautomata
+1
vote
1
answer
11
Self doubt
No of JK / T FFs needed to design synchronous counter for sequence 1,4,2,3,1,4,2,3,1,4...
asked
Nov 9, 2018
in
Digital Logic
by
jatin khachane 1
Loyal
(
6.4k
points)

68
views
digitallogic
digitalcounter
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votes
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answers
12
Sequential Circuits  Counters
A mod2 counter followed by a mod5 counter is a) Same as mod5 counter followed by mod2 counter b) A decade counter c) A mod7 counter d) None
asked
Nov 3, 2018
in
Digital Logic
by
garvit_vijai
(
207
points)

75
views
digitalcircuits
sequentialcircuit
digitalcounter
0
votes
0
answers
13
synchronous counters
What will be the output frequency of a 10 bit ring counter if the input frequency is 1500k Hz. Kindly explain using diagram.
asked
Oct 22, 2018
in
Digital Logic
by
Kaushal Sanadhya
(
93
points)

36
views
digitalcounter
0
votes
2
answers
14
Synchronous Counter Circuit
In the given synchronous Counter circuit, initially all Outputs are Reset. It is required to replace FF2 with AB Flip Flop. The FF2 inputs would be: A. A = Q1 and B = Q1' B. A = Q1' and B = Q1' C. A = Q1.Q0 and B = Q1.Q0 D. A = Qo' and B = Qo'
asked
Oct 10, 2018
in
Digital Logic
by
Na462
Loyal
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8.6k
points)

54
views
digitallogic
synchronousasynchronouscircuits
digitalcounter
0
votes
0
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15
virtualgate
asked
Oct 9, 2018
in
Digital Logic
by
Dharmendra Lodhi
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3.3k
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51
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virtualgate
digitalcounter
0
votes
1
answer
16
Digital electronics
asked
Oct 6, 2018
in
Digital Logic
by
pilaniya
(
7
points)

34
views
digitalcounter
0
votes
0
answers
17
Synchronous Counter
asked
Oct 1, 2018
in
Digital Logic
by
Na462
Loyal
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8.6k
points)

55
views
digitallogic
synchronousasynchronouscircuits
digitalcounter
0
votes
1
answer
18
Counter
A MOD2 ripple counter is cascaded with a MOD8 synchronous counter. The resulting circuit will form a counter of MOD = ___________. ____________________________________________________________________ my problem is how can a asynchronous counter work like an synchronous counter? diagram required with explanation for clearity
asked
Aug 26, 2018
in
Digital Logic
by
srestha
Veteran
(
108k
points)

186
views
digitallogic
digitalcounter
+1
vote
0
answers
19
Johnson Counter Doubt
I have found this statement about Johnson Counter : A Johnson counter requires decoding gates whereas a ring counter doesn't. As with the binary counter, one logic gate (AND gate) is required to decode each state, but with the Johnson counter, each ... to implement it? The reference link is here: https://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#johnson
asked
Jul 27, 2018
in
Digital Logic
by
dan31
Junior
(
657
points)

36
views
digitallogic
digitalcounter
0
votes
1
answer
20
UGC NET July 2018 Q 94
asked
Jul 10, 2018
in
Digital Logic
by
Sanjay Sharma
Veteran
(
50.5k
points)

230
views
sequentialcircuit
digitalcounter
0
votes
1
answer
21
Asynchronous counter
according to me the answer should be 6 but is 7 pls explain
asked
Jun 19, 2018
in
Digital Logic
by
Tarun322
(
31
points)

105
views
digitalcounter
asynchronouscounter
upcounter
0
votes
1
answer
22
Counter
Answer given is 4 but mine is 2
asked
May 22, 2018
in
Digital Logic
by
ajaysoni1924
(
179
points)

66
views
digitallogic
digitalcounter
flipflop
0
votes
1
answer
23
Counters
I didn't understand the concept of Counters well Can anybody provide any online Source or Explain the Concept of Counter which includes Johnson Counter and what is meant by mod 3,mod 6 etc Counters ?
asked
Apr 17, 2018
in
Digital Logic
by
Na462
Loyal
(
8.6k
points)

85
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digitalcounter
0
votes
0
answers
24
GFG question 2018
Consider following counters: Counter1: Counter2: Which of the following option is correct? (A) Counter1 is a threebit counter which counts 0, 1, 2, 4, 5, 7, 0, . and Counter2 is a threebit counter which counts 0, 3, 6, 1, 4, 7, 2, 5, 0, 3, . (B) Counter1 is a ... 6, 1, 4, 7, 2, 5, 0, 3, . and Counter2 is a threebit counter which counts 0, 1, 2, 3, 5, 6, 0, .
asked
Feb 1, 2018
in
Digital Logic
by
Utsav09
Active
(
1.3k
points)

123
views
digitallogic
digitalcounter
+2
votes
1
answer
25
Digital01
MOD Value ? FF clears at $Q_{3}Q_{2}Q_{1}$ = 110 So mod value is 6 ...??
asked
Jan 17, 2018
in
Digital Logic
by
Anjan
Active
(
1.7k
points)

114
views
digitallogic
digitalcounter
0
votes
0
answers
26
self doubt
does synchronous counters act as frequency dividers? if input frequency to a 5 bit johnson counter is 500 hz what is the output frequency ?
asked
Jan 15, 2018
in
Digital Logic
by
Venkat Sai
Active
(
3.7k
points)

58
views
digitallogic
digitalcounter
+2
votes
0
answers
27
Counter
Find the Mod Value for the counter My ans is MOD5 counter but given is MOD3 please explain ....
asked
Jan 11, 2018
in
Digital Logic
by
Anjan
Active
(
1.7k
points)

144
views
digitallogic
digitalcounter
0
votes
0
answers
28
Time Calculation in counters
Describe the steps with plausible assertions.
asked
Dec 24, 2017
in
Digital Logic
by
ashwina
Active
(
2.1k
points)

79
views
digitalcounter
0
votes
0
answers
29
Digital Logic: Counters
Consider the following question: My explanation: A clock cycle time should be large enough that all flipflops can come in a stable state before the next clock cycle starts. Suppose cycle 1 is just completed and cycle 2 is just about to start: 1. to ... on the following link, it is $\frac{1}{20ns}$. Can someone explain, please? https://gateoverflow.in/26442/gate1991_5c
asked
Dec 18, 2017
in
Digital Logic
by
Manu Thakur
Boss
(
42.6k
points)

105
views
digitalcounter
digitalcircuits
flipflop
0
votes
1
answer
30
MADE EASY test series DIGITAL LOGIC  Synchronous counters
Consider the following synchronous counter made up of JK,D,T flip flops as in the image! now here why J is taken as Q0' (complement) instead of Q0'' (double complement) you can clearly see a bubble and a q0' ... as it should be so q0'' right? please clarify!
asked
Dec 14, 2017
in
Digital Logic
by
vishnu priyan
(
431
points)

263
views
digitalcircuits
madeeasytestseries
flipflop
sequential
digitalcounter
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Is there any option that the answer can be 3 or 4?
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Yes sir, and if we solve, it'll be 4.00
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