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NIELIT 2021 Dec Scientist B - Section B: 2
Consider the following $2$ bit counter using $\text{T}$ flip-flops following $0-2-3-1-0$ sequence. What should be the value of $x$?  $\text{Q}_{2}$$\text{Q}_{1}+\text{Q}_...
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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 21
Consider the sequential circuit shown in the figure, where both flip-flops “$\text{FD A}$” and “$\text{FD B}$” used are positive edge-triggered $D$ flip-flops. The state ...
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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 22
Consider the sequential circuit shown in the figure, where both flip-flops “$\text{FD A}$” and “$\text{FD B}$” used are positive edge-triggered $D$ flip-flops. The state ...
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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 23
Consider the following circuit.What are the values of $P, Q, R$ after two cycles if $P=0, Q=1$ and $R=0$ to begin with?$011$$101$$100$$111$
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GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 25
Consider the following circuit.$10011000010$ is supplied to the "data" terminal in $11$ clock cycles. After that the values of $q_2 q_1 q_0$ are$000$$010$$101$$111$
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Made Easy Test Series Question
The frequency of the pulse at D is __________ Hz.
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Made Easy Test Series Question
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.
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GATE CSE 2021 | Set 1 | Question: 28
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below:Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next thre...
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NIELIT 2017 OCT Scientific Assistant A (IT) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple cou...
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NIELIT 2017 OCT Scientific Assistant A (CS) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple cou...
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UGC NET CSE | December 2007 | Part 2 | Question: 8
In order to build a $\text{MOD - 18}$ counter, the minimum number of flip flops needed is equal to :$18$$9$$5$$4$
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UGC NET CSE | June 2007 | Part 2 | Question: 10
What is the maximum counting speed of a $4$-bit binary counter which is composed of Flip-Flop with a propagation delay of $25\:ns$?$1 \text{MHz}$$10 \text{MHz}$$100 \text...
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UGC NET CSE | June 2019 | Part 2 | Question: 15
What will be the number of states when a MOD-$2$ counter is followed by a MOD-$5$ counter?$5$$10$$15$$20$
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Morris Mano Edition 3 Exercise 7 Question 32 (Page No. 305)
Construct a Johnson counter for ten timing signals.
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Morris Mano Edition 3 Exercise 7 Question 31 (Page No. 305)
Complete the design of Johnson counter of the figure showing the output of the eight timing signals using eight AND gates.
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Morris Mano Edition 3 Exercise 7 Question 27 (Page No. 305)
Using two circuits of the type shown in the figure, construct a binary counter that counts from 0 through binary 64.
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Morris Mano Edition 3 Exercise 7 Question 26 (Page No. 305)
Construct a mod -12 counter using the circuit specified in the figure.
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