1 1 vote A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns Digital Logic nielit2017oct-assistanta-it digital-logic sequential-circuit flip-flop digital-counter + – admin 1.7k views answer comment Share Follow Print See 1 comment 1 1 comment reply Lakshman Bhaiya commented Jun 25, 2022 reply Follow flag https://gateoverflow.in/344429/Nielit-2017-oct-scientific-assistant-a-cs-section-d-10 0 0 replyShare Please log in or register to add a comment.
0 0 votes option (b) is correct. for rippel counter:- $T_{delay}$=nx$T_{ff}$+$T_{cc}$ for synchronous counter:- $T_{delay}$=$T_{ff}$+$T_{cc}$ mohit rathore answered Sep 8, 2020 mohit rathore comment Share Follow 0 reply Please log in or register to add a comment.
0 0 votes For Ripple Counter for $2^n$ state no of Flipflop required is n. As this is async counter so Delay = $N*Propagation Delay$ so $4*10 ms = 40 ms$ For Sync Counter Delay = $1*Propagation Delay$ as Sync counter has Clock same clock Hence $Delay = 10ms$ Correct Ans is: $B$ AnkanG answered Dec 16, 2020 AnkanG comment Share Follow 0 reply Please log in or register to add a comment.
0 0 votes B is the answer. Time delay is constant since it’s synchronous. Ripple will be 10 + 10 + 10 + 10 = 40 goldenface answered Feb 1, 2021 goldenface comment Share Follow 0 reply Please log in or register to add a comment.
0 0 votes ANS : B R=40R=40 ns, S=10S=10 ns anjli answered Feb 6, 2021 anjli comment Share Follow 0 reply Please log in or register to add a comment.