edited by
4,105 views
6 votes
6 votes

Consider the logic circuit given below:

$\text{Q =}$ __________?

  1. $\overline{\text{A}} \text{C} + \text{B} \overline{\text{C}} +\text{CD}$
  2. $\text{ABC} + \overline{\text{C}} \text{D}$
  3. $\text{AB + B} \overline{\text{C}} + \text{B} \overline{\text{D}}$
  4. $\text{A} \overline{\text{B}} + \text{A} \overline{\text{C}} + \overline{\text{C}} \text{D}$
edited by

6 Answers

Answer:

Related questions

9 votes
9 votes
5 answers
1
go_editor asked Jul 1, 2016
5,436 views
Consider the logic circuit given below.The inverter, AND and OR gates have delays of $6, 10$ and $11$ nanoseconds respectively. Assuming that wire delays are negligible, ...
10 votes
10 votes
3 answers
2
focus _GATE asked Jul 17, 2015
12,606 views
What are the final values of $\text{Q}_1$ and $\text{Q}_0$ after $4$ clock cycles, if initial values are $00$ in the sequential circuit shown below:$11$$01$$10$$00$
7 votes
7 votes
3 answers
3
go_editor asked Jul 1, 2016
3,864 views
The output of a tristate buffer when the enable input in $0$ isAlways $0$Always $1$Retains the last value when enable input was highDisconnected state
8 votes
8 votes
4 answers
4
Isha Gupta asked Jun 23, 2016
4,211 views
Which of the following is not valid Boolean algebra rule?$\text{X.X = X}$$\text{(X+Y).X = X}$$\overline{X}+\text{XY = Y}$$\text{(X+Y).(X+Z) = X + YZ}$