A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 106 instructions per second. An average instruction requires six processor cycles, three of which use the memory bus. A memory read or write operation uses one processor cycle. Suppose that the CPU is continuously executing “background” programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose that very large blocks of data are to be transferred between M and D.
Calculate I/O data transfer rate, in words per second possible through D if DMA transfer is used [ Assume that the DMA module can use all of these cycles, and ignore any setup or status‐checking time] ?
- 2.15 x 106
- 3.15 x 106
- 1.15 x 106
- 4.15 x 106
