0 votes 0 votes Please explain Digital Logic sequential-circuit + – SKMAKM asked Aug 5, 2022 SKMAKM 536 views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
2 votes 2 votes Assuming all the flip flops are initially high, This is a low level triggered clock, J-K flip flop has both the input as 1 i.e. in toggle mode . all the j-k flip will toggle on their negative clock cycle . . JAINchiNMay answered Aug 6, 2022 JAINchiNMay comment Share Follow See all 3 Comments See all 3 3 Comments reply ankitgupta.1729 commented Aug 6, 2022 reply Follow Share There is a small bubble at the bottom of the each flip flop which is connected with the NAND gate. Could you please tell, is it some kind of control input like clear or preset ? 0 votes 0 votes JAINchiNMay commented Aug 6, 2022 reply Follow Share It must be clear 0 votes 0 votes ankitgupta.1729 commented Aug 6, 2022 reply Follow Share If it is clear or preset then would not it affect the output as compared to when these control inputs are not present and also, unable to understand why the waveform for clear input is present below the options for the given question. 1 votes 1 votes Please log in or register to add a comment.