Gate@Zeal 2023 Test Series

Question

Please explain

Answer 1

Assuming all the flip flops are initially high,
This is a low level triggered clock,
J-K flip flop has both the input as 1 i.e. in toggle mode . 

all the j-k  flip will toggle on their negative clock cycle .
.

Comments

There is a small bubble at the bottom of the each flip flop which is connected with the NAND gate. Could you please tell, is it some kind of control input like clear or preset ?

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It must be clear

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If it is clear or preset then would not it affect the output as compared to when these control inputs are not present and also, unable to understand why the waveform for clear input is present below the options for the given question.