Assume the 5-stage MIPS pipeline(IF, ID, EX, MEM, and WB) with no forwarding, and each stage takes 1 cycle. Instead of inserting nops, you let the processor stall on hazards.
The functionality of the five stages of this pipeline is as follows :
1. Instruction fetch (IF) - get instruction from memory, increment PC
2. Instruction Decode (ID) - translate opcode into control signals and read registers
3. Execute (EX) - perform ALU operation, compute jump/branch targets
4. Memory (MEM) - access memory if needed
5. Writeback (WB) - update register file (write back to register file)
The pipeline does not have other bypassing/forwarding hardware.
All Instructions, including loads and stores, spend only one cycle in each stage. The register file can be written and then read in the same cycle.
Consider the following sequence of instructions executed on this pipeline:
1. lw $s2,0($s1)
2. lw $s1, 40($s6)
3. sub $s6, $s1, $s2
4. add $s6, $s2, $s2
5. or $s3, $s6, $zero
6. sw $ s6, 50($s1)
What is the execution time (in cycles) for the whole program?
