- $VA = 32\; bits$
- $PA = 32\; bits$
- $\text{Page size} = 4\;KB = 2^{12} B$
- $PTE = 4 \ B$

Since page size is $4$ KB we need $\lg 4K = 12 $ bits as offset bits.

It is given that Equal number of bits should be used for indexing first level and second level page table. So, out of the remaining $32-12 = 20$ bits $10$ bits each must be used for indexing into first level and second level page tables as follows:

**B**) Since $10$ bits are used for indexing to a page table, number of page table entries possible $=2^{10} = 1024.$ This is same for both first level as well as second level page tables. ^{ }

C)

Frame no $= 32$ bit (Physical Address) $- 12$ (Offset) $= 20$

No. of bits available for Storing Protection and other information in second level page table

$= 4 \times 8 - 20$

$= 32-20 = 12\;Bits$

No. of bits in first level page table to address a second level page table is $\log_2$ of

$\frac{\text{Physical memory size}}{\text{#Entries in a Second level page table $\times$ PTE size}}$

$=\log_2 \left[\frac{2^{32}}{2^{10} \times 4}\right]$

$=\log_2 \left(2^{20}\right)$

$=20\; bits.$

So here also, the no. of bits available for Storing Protection and other information $=32-20 =12\; bits.$