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Recent questions tagged virtual-memory

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A computer uses $46$-bit virtual address, $32$-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table $(T1)$, which occupies exactly one page. Each entry of $T1$ stores the base address of a page of ... cache block size is $64$ bytes. What is the size of a page in $KB$ in this computer? $2$ $4$ $8$ $16$
asked Mar 30, 2020 in Operating System Lakshman Patel RJIT 346 views
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A computer uses $46-bit$ virtual address, $32-bit$ physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table ($T1$), which occupies exactly one page. Each entry of $T1$ stores the base ... needed to guarantee that no two synonyms map to different sets in the processor cache of this computer? $2$ $4$ $8$ $16$
asked Mar 30, 2020 in Operating System Lakshman Patel RJIT 233 views
4 votes
3 answers
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Which of the following is incorrect for virtual memory? Large programs can be written More I/O is required More addressable memory available Faster and easy swapping of process
asked Mar 24, 2020 in Operating System jothee 303 views
19 votes
9 answers
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Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $\textsf{TLB}$ lookup takes $20$ ns. Each page transfer to/from the disk takes $5000$ ns. ... disk. $\textsf{TLB}$ update time is negligible. The average memory access time in ns (round off to $1$ decimal places) is ___________
asked Feb 12, 2020 in Operating System Arjun 18.2k views
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0 answers
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Write a program that demonstrates the effect of $TLB$ misses on the effective memory access time by measuring the per-access time it takes to stride through a large array. Explain the main concepts behind the program, and describe what you expect the output to ... . Repeat part $(b)$ but for an older computer with a different architecture and explain any major differences in the output.
asked Oct 26, 2019 in Operating System Lakshman Patel RJIT 165 views
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0 answers
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A computer with an $8-KB$ page, a $256-KB$ main memory, and a $64-GB$ virtual address space uses an inverted page table to implement its virtual memory. How big should the hash table be to ensure a mean hash chain length of less than $1?$ Assume that the hash table size is a power of two.
asked Oct 26, 2019 in Operating System Lakshman Patel RJIT 85 views
1 vote
1 answer
9
You are given the following data about a virtual memory system: The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$ A page table entry can be found in $100$ clock cycles or $100\: nsec.$ The average page replacement time is $6\: msec.$ ... by the $TLB\:\: 99\%$ of the time, and only $0.01\%$ lead to a page fault, what is the effective address-translation time?
asked Oct 26, 2019 in Operating System Lakshman Patel RJIT 144 views
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The Intel $8086$ processor did not have an MMU or support virtual memory. Nevertheless, some companies sold systems that contained an unmodified $8086$ CPU and did paging. Make an educated guess as to how they did it. (Hint: Think about the logical location of the MMU.)
asked Oct 26, 2019 in Operating System Lakshman Patel RJIT 93 views
0 votes
1 answer
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Consider a computer system that has cache memory, main memory (RAM) and disk, and an operating system that uses virtual memory. It takes $1$ nsec to access a word from the cache, $10$ nsec to access a word from the RAM, and $10$ ms to access a word from the disk. If the cache hit rate is $95\%$ and main memory hit rate (after a cache miss) is $99\%$, what is the average time to access a word?
asked Oct 23, 2019 in Operating System Lakshman Patel RJIT 196 views
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