There is space for 2 rows in one page frame, so If the architecture stores the array in row major order,
The 'a' part code would require 50 page faults x 100 times = 5000 page faults.
Because in one complete iteration of the i loop, 100 different rows are accessed, since 2 rows are in one frame 50 times page fault will happen. And this happen for all the 100 column ( outer j loop). Thus 5000 faults.
But for 'b' code, 100 column are accessed of the same row, by the inner j loop, so no faults for column, only faults will be while trying to access different rows. again that will be only 50, since 2 rows are stored in a page, so always 2 adjacent rows will be available.
Also since we use LRU, the page for the instruction fetching will always stay in the memory, Because it is used in every instructions. Only the 2nd and 3rd pages be swapped for the matrix data storing.