Recent questions tagged paging

A system uses:$4$ KB pages A $4$-entry fully associative TLB LRU replacement $$ \textbf{Initial TLB:} $$$$\begin{array}{|c|c|c|c|}\hline\text{Valid} & \text{VPN} & \text{...

Assume a task is divided into $8$ equal-sized segments, and page tables have $4$ entries.Thus, the system has a combination of segmentation and paging.Assume also that th...

Consider a three-level page table on a system where:Page size $=256$ bytesPage-table entry size $=2$ bytesFirst-level page tables contain $16$ entriesSecond-level page ta...

Consider a virtual memory system that uses 2-level paging.The page size is: $256=2^8$ bytesEach individual page table fits exactly into one memory frame, and the size of ...

A byte-addressable machine implements virtual memory with a $4$ MB virtual address space using a three-level page-table system.All page tables live in physical address sp...

The following table shows some parameters of a virtual memory system:$$\begin{array}{|c|c|} \hline\text{Parameter} & \text{Value} \\\hline\text{Virtual Address} & 42\ \te...

Consider a system with:Two-level page tables$42$-bit virtual addresses$40$-bit physical addresses $8$-byte page-table entries $64$ KB pages $64$ KB page tables at each le...

Let us assume there is a two-level page table in your system.The virtual address is split as:$\texttt{<vpn part1, vpn part2, page offset>}$Which of the following statemen...

Consider a system using a two-level page table. Assume the required page is present in physical memory.How many main-memory accesses are required for a virtual-address ac...

The following virtual-to-physical address translations are observed for a process. All addresses are $32$ bits long.\[\begin{array}{c|c}\text{Virtual address} & \text{Phy...

Which of the following statements about multi-level page tables are correct?A multi-level page table may consume more pages than a linear page table for some address-spac...

A processor experiences a TLB miss while translating an address using a two-level page table.What is the number of main-memory accesses required only for the page-table l...

A system has:$15$-bit virtual addresses Page size $=32$ bytes A two-level page table One-byte PDEs and PTEs Entry format: one valid bit followed by a $7$-bit physical-fra...

Which statement correctly describes the purpose of the valid bit in a page-table entry?It indicates whether the page has been modified. An invalid-bit access causes the p...

Consider the following page table:$$\begin{array}{|c|c|}\hline\text{Virtual page} & \text{Frame} \\\hline0 & 3 \\\hline1 & 10 \\\hline2 & 9 \\\hline3 & 2 \\\hline4 & 0 \\...

A system uses paging to implement virtual memory and uses a simple linear page table.The system has:Virtual-address space $=1\text{ GB}=2^{30}$ bytes Page size $=1\text{ ...

Consider a single-level paging system with:$12$-bit virtual addresses $24$-bit physical addresses Page size $=256=2^8$ bytes What is the maximum number of entries in the ...

Consider a virtual-memory system that uses paging.$\text{Virtual address length } = 32 \text{ bits}$ $\text{Physical address length } = 32 \text{ bits}$ $\text{Page size ...

Consider the following page table. All numbers are expressed in base $10$.$$\begin{array}{|c|c|}\hline\text{Virtual page} & \text{Frame} \\\hline0 & 3 \\\hline1 & 10 \\\h...

A system has a Translation Lookaside Buffer (TLB) that has a reach of $1$ MB. TLB reach is defined as the total amount of physical memory that can be accessed through the...