Recent questions tagged paging / GATE Overflow for GATE CSE

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121

APPLIED AI TEST 2
Consider the following memory Architecture of a Machine in the following Table Virtual Address 54 bits Page size 16K bytes PTE size 4 bytes Assume that there are 8 bits reserved for the Os functions(protection,valid, modified,and Hit/Miss-all overhead bits) other than required by the ... for the application data and code ? 2^26 byte 2^40 bytes 2^38- 2^26 bytes 2^40 - 2^38 bytes

Consider the following memory Architecture of a Machine in the following TableVirtual Address54 bitsPage size16K bytesPTE size4 bytesAssume that there are 8 bits reserved...

codingo1234

396 views

codingo1234 asked Jan 9, 2019

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0 answers

122

UPPCL AE 2018:61
Consider a computer system with $32-$ bit virtual addressing and page size of sixty-four kilobytes. The computer system has one-level page table per process with each page table entry of $6$ bytes. If the maximum physical memory size supported by this paging system is ... how many bits can be used for flags and permissions within a page table entry? $6$ None of the above $7$ $5$

Consider a computer system with $32-$ bit virtual addressing and page size of sixty-four kilobytes. The computer system has one-level page table per process with each pag...

admin

300 views

admin asked Jan 5, 2019

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1 answer

123

Relation between physical address, logical address and relocation register
Physical address is (A) The logical address added by the value in re-locatable registers (B) Re location register – logical address (C) Re location address + relocation register (D) None of these

Physical address is(A) The logical address added by the value in re-locatable registers(B) Re location register – logical address(C) Re location address + relocation re...

Raj Singh 1

5.0k views

Raj Singh 1 asked Jan 3, 2019

0 votes

3 answers

124

MadeEasy Test Series: Operating System - Memory Management

Ramij

954 views

Ramij asked Dec 26, 2018

0 votes

1 answer

125

madeeasy OS 2019- Memory overhead multilevel paging
for memory overhead in Multi level paging, for innermost table only 1 page size shall be counted na? and NOT the complete page table size? please explain the concept, thanks!

for memory overhead in Multi level paging, for innermost table only 1 page size shall be counted na? and NOT the complete page table size?please explain the concept, than...

Markzuck

1.4k views

Markzuck asked Dec 22, 2018

1 votes

1 answer

126

Os TLB question
How they calculated time for number of levels?

How they calculated time for number of levels?

muthu kumar

1.4k views

muthu kumar asked Dec 16, 2018

0 votes

1 answer

127

multilevel paging

Rahul_Rathod_

734 views

Rahul_Rathod_ asked Dec 15, 2018

1 votes

0 answers

128

selfsoubt ME OTS
consider a paged virtual memory management system having 32 bit virtual addresses with page size 1 KB .each page table entry required 32 bits.It is desired to limit the page table size into one page .if Suresh uses smaller page size at the first level of page table hierarchy ,then the number of pages needed are _?? answer given as 65793 my answer -16449. please verify

consider a paged virtual memory management system having 32 bit virtual addresses with page size 1 KB .each page table entry required 32 bits.It is desired to limit the p...

Prateek Raghuvanshi

520 views

Prateek Raghuvanshi asked Dec 14, 2018

2 votes

1 answer

129

MadeEasy Subject Test 2019: Operating System - Virtual Memory

jatin khachane 1

498 views

jatin khachane 1 asked Dec 13, 2018

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0 answers

130

ME Test Series

Shadan Karim

164 views

Shadan Karim asked Dec 11, 2018

2 votes

2 answers

131

MadeEasy Test Series: Operating System - Memory Management
Consider a paging scheme, in which average process size is 32MB and each page table entry size is 4B. The optimal size of page to minimize the total overload due to page table and internal fragmentation is _______KB.

Consider a paging scheme, in which average process size is 32MB and each page table entry size is 4B. The optimal size of page to minimize the total overload due to page ...

balraj_allam

1.7k views

balraj_allam asked Dec 6, 2018

0 votes

1 answer

132

TLB OS
Why the formula used here is not P(10) + (1-P)(50) = 20 ?; A computer keeps its page tables in memory. The time required to read a word from the page table is 50ns. To reduce this overhead, the computer has a TLB, which holds 32 (virtual page, physical page frame) pairs and can ... : 10ns + (1 - p) 50ns = 20ns p =4/5 = .80 The TLB hit rate has to be 80% for a mean access time of 20ns.

Why the formula used here is not P(10) + (1-P)(50) = 20 ?;A computer keeps its page tables in memory. The time required to read a word from the pagetable is 50ns. To redu...

rahuljai

1.3k views

rahuljai asked Dec 3, 2018

0 votes

3 answers

133

OS-Virtual Memory
A computer system has a page size of 1024 bytes and maintains page table for each process in the main memory.The overhead required for doing a lookup in the page table is $500ns$.To reduce this overhead, the computer has a TLB that caches 32 ... mappings.A TLB lookup requires $100ns$.What TLB hit-rate is required to ensure an average virtual address translation time of $200ns$?

A computer system has a page size of 1024 bytes and maintains page table for each process in the main memory.The overhead required for doing a lookup in the page table is...

Ayush Upadhyaya

1.2k views

Ayush Upadhyaya asked Dec 2, 2018

0 votes

1 answer

134

ace test series
A computer whose processes have 1024 pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is 500 nsec. To reduce this overhead, the computer has tlb which holds 32 entries and can do look up in 100 nsec. What hit rate is needed to reduce the mean overhead to 200 nsec? can anyone solve this

A computer whose processes have 1024 pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is 500 ns...

vijju532

766 views

vijju532 asked Nov 28, 2018

1 votes

1 answer

135

Paging and TLB
A translational look aside buffer is a hardware device used for speeding up the conversation from virtual address to physical address. Consider a memory management unit where a memory reference takes 500 nanoseconds; TLB (Translation Look aside Buffer) reference takes 40 ... 80%. The speed-up (in %) we gained using TLB technique compared to the pure paging with no TLB ________.

A translational look aside buffer is a hardware device used for speeding up the conversation from virtual address to physical address. Consider a memory management unit w...

Shivangi Parashar 2

1.5k views

Shivangi Parashar 2 asked Nov 27, 2018

0 votes

0 answers

136

raman classes test series
.. an getting 0.00010650

..an getting 0.00010650

Gate Fever

334 views

Gate Fever asked Nov 13, 2018

0 votes

0 answers

137

Paging
Consider a system with page size 2^13 bytes , a2 level page table organization PTE size 32 bits with following format. Bit0: present bit Bit1:valid bit Bit2:dirty bit Bit6-29: physical frame no. Other bits insignificant. If last level PTE for the virtual address 0x12345678 has value 0x103 and processor trying to read a inst. From that address.what memory address will be read?

Consider a system with page size 2^13 bytes , a2 level page table organization PTE size 32 bits with following format.Bit0: present bitBit1:valid bitBit2:dirty bitBit6-29...

rishabhdevsingh1

405 views

rishabhdevsingh1 asked Oct 31, 2018

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0 answers

138

Memory Overhead
What is memory overhead? Is it's size same as size of page table for the process?

What is memory overhead? Is it's size same as size of page table for the process?

srestha

1.5k views

srestha asked Oct 29, 2018

3 votes

3 answers

139

Multilevel paging
Consider a machine with byte addressable memory 32 bits virtual addresses, 32 bits physical addresses and 4 KB page size. If a two-level page table system is used where each page table occupies one page and page table entries of 4 B each. How to calculate the size of 1st level page table & 2nd level page table(s) ? Also how to calculate memory overhead?

Consider a machine with byte addressable memory 32 bits virtual addresses, 32 bits physical addresses and 4 KB page size. If a two-level page table system is used where e...

Lovejeet Singh

3.0k views

Lovejeet Singh asked Oct 22, 2018

0 votes

1 answer

140

Paging - Memory management
Why do we need multilevel paging? According to me the reason is that page table needs contiguous memory allocation.So if page table size is too large, we may not be able to store the table in contiguous memory. So is this the reason behind multilevel paging? Also when we page the page table, do we store all levels page table in memory or only the outer level page table?

Why do we need multilevel paging?According to me the reason is that page table needs contiguous memory allocation.So if page table size is too large, we may not be able t...

Lovejeet Singh

616 views

Lovejeet Singh asked Oct 17, 2018

1 votes

2 answers

141

AceBook
Consider the machine with 64 MB Physical Memory and a 34 bit Virtual Address Space. If the page size is 4KB, the appropriate sizes of conventional and inverted page table sizes are: a) 4M, 4K b)4K, 4M c)4M, 16K d)16K, 4M. soln: is Option C. but my ans is (7MB, 28KB)

Consider the machine with 64 MB Physical Memory and a 34 bit Virtual Address Space. If the page size is 4KB, the appropriate sizes of conventional and inverted page table...

abhishek1995_cse

1.7k views

abhishek1995_cse asked Oct 16, 2018

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0 answers

142

self doubt os
Assume we are dealing with multilevel page table here Page Size is 4KB, Page table entry is 4B and the outer page table size is 256B then if the no of levels is 1 so Virtual Address is= 256 KB. but when there are 2 levels of paging then please check my procedure to ... but how to get offset?? here 6 is no of bit in outer table of second split and 10 is the no of bit in first split.

Assume we are dealing with multilevel page table here Page Size is 4KB, Page table entry is 4B and the outer page table size is 256B then if the no of levels is 1 so V...

Divyanshum29

315 views

Divyanshum29 asked Oct 15, 2018

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0 answers

143

Paging
While converting the logical address into physical address through paging why do we need to load the entire page table into the main memory?

While converting the logical address into physical address through paging why do we need to load the entire page table into the main memory?

Iamniks4

352 views

Iamniks4 asked Oct 6, 2018

0 votes

1 answer

144

Paging advantage
Advantage of paging: It support time sharing system..... Explain plz can't get it

Advantage of paging: It support time sharing system..... Explain plz can't get it

akankshadewangan24

385 views

akankshadewangan24 asked Oct 2, 2018

0 votes

2 answers

145

Memory overhead in Multilevel paging with TLB
Consider a computer system using 2-level paging with TLB.The logical address supported is 32 bits.The page table is divided into 512 pages each of size 1K.The memory access time is 100ns and the TLB access time 15ns .Page table entry size at 1st ... page table along with the page of the second level page table for a process? A)6KB B)4KB C)5KB D)12KB

Consider a computer system using 2-level paging with TLB.The logical address supported is 32 bits.The page table is divided into 512 pages each of size 1K.The memory acce...

Deepanshu

1.7k views

Deepanshu asked Oct 1, 2018

1 votes

1 answer

146

Virtual Memory

Na462

735 views

Na462 asked Sep 29, 2018

2 votes

0 answers

147

Multi-level paging doubt
Consider a computer system using 2-level paging with TLB. The logical address supported is 32 bits. The page table is divided into 512 pages each of size 1KB. Page table entry size at 1st level is 2Bytes and that at the second level is 4 Bytes each. ... level PT)+$512*1KB$(At second level)=$544KB$ Is my analysis correct? Below is the visualisation what I see is happening.

Consider a computer system using 2-level paging with TLB. The logical address supported is 32 bits. The page table is divided into 512 pages each of size 1KB. Page table ...

Ayush Upadhyaya

977 views

Ayush Upadhyaya asked Sep 28, 2018

1 votes

1 answer

148

Multilevel Paging

Vishnathan

805 views

Vishnathan asked Sep 15, 2018

0 votes

1 answer

149

Page Table
A page table based translation will always consume less memory to store translation meta-data, than a seg-mentation based solution. True/False. Explain.

A page table based translation will always consume less memory to store translation meta-data, than a seg-mentation based solution. True/False. Explain.

dd

402 views

dd asked Sep 13, 2018

1 votes

2 answers

150

Memory Management : paging
Consider a system using 2 level paging applicable page table is devided into 2k pages each size 4kB. If PAS is 64 MB which is devided into 16K frames . PTE size is 2B in both the levels calculate the length of PA, LA and # of entry at second level?

Consider a system using 2 level paging applicable page table is devided into 2k pages each size 4kB. If PAS is 64 MB which is devided into 16K frames . PTE size is 2B in...

Aks9639

1.4k views

Aks9639 asked Sep 10, 2018

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