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Recent questions tagged nielit2017july-scientistb-cs
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NIELIT 2017 July Scientist B (CS) - Section B: 1
What does the following function do for a given Linked List with first node as head? void fun1(struct node* head) { if(head==NULL) return ... list in reverse orderPrints alternate nodes of Linked ListPrints alternate nodes in reverse order
admin
2.1k
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admin
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Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
linked-list
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1.2k
views
0
answers
0
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NIELIT 2017 July Scientist B (CS) - Section B: 2
Which of the following statements is/are TRUE for an undirected graph?Number of odd degree vertices is evenSum of degrees of all vertices is evenP onlyQ onlyBoth P and QNeither P nor Q
admin
1.2k
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admin
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Mar 30, 2020
Graph Theory
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
degree-of-graph
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1.7k
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0
answers
4
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NIELIT 2017 July Scientist B (CS) - Section B: 3
Consider the following function that takes reference to head of a Doubly Linked List as parameter. Assume that a node of doubly linked list has ...
admin
1.7k
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admin
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Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
linked-list
+
–
1.3k
views
4
answers
2
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NIELIT 2017 July Scientist B (CS) - Section B: 4
Let $A$ be a square matrix of size $n\times n$. Consider the following program. What is the expected output?C=100 for i=1 to n do for j=1 to ... upper diagonal elements and subtracting $100$ from diagonal elements of $A$.None of the option.
admin
1.3k
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admin
asked
Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
array
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6.7k
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2
answers
2
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NIELIT 2017 July Scientist B (CS) - Section B: 5
Following is C like Pseudo code of a function that takes a number as an argument, and uses a stack S to do processing. void fun(int n) { Stack S;//Say it ... Prints the value of $\log n$.Prints the value of $\log n$ in reverse order.
admin
6.7k
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admin
asked
Mar 30, 2020
Programming in C
nielit2017july-scientistb-cs
programming-in-c
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1.3k
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3
answers
4
votes
NIELIT 2017 July Scientist B (CS) - Section B: 6
Assume that the operators $+,-,\times$ are left associative and $\wedge$ is right associative. The order of precedence(from highest to lowest) is $\wedge,\times, +,-$. ... $-+a\times bc\wedge\wedge def$
admin
1.3k
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admin
asked
Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
stack
infix-prefix
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–
6.8k
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2
answers
3
votes
NIELIT 2017 July Scientist B (CS) - Section B: 7
A balance factor in AVL tree is used to checkwhat rotation to makeif all child nodes are at same levelwhen the last rotation occurredif the tree is unbalanced
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6.8k
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admin
asked
Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
avl-tree
easy
+
–
1.1k
views
2
answers
2
votes
NIELIT 2017 July Scientist B (CS) - Section B: 8
A priority queue is implemented as a Max-Heap. Initially, it has $5$ elements. The level-order traversal of the heap is: $10,8,5,3,2$. Two new elements $1$ and $7$ are inserted into the ... 5$10,8,7,2,3,1,5$10,8,7,1,2,3,5$10,8,7,5,3,2,1$
admin
1.1k
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admin
asked
Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
priority-queue
binary-heap
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874
views
1
answers
2
votes
NIELIT 2017 July Scientist B (CS) - Section B: 9
The worst case running times of Insertion sort, Merge sort and Quick sort, respectively, are$\Theta(n \log n),\Theta(n \log n) \text{ and } \Theta(n^2)$\Theta(n^2),\Theta(n ... n \log n)$\Theta(n^2),\Theta(n\log n) \text{ and } \Theta(n^2)$
admin
874
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admin
asked
Mar 30, 2020
Algorithms
nielit2017july-scientistb-cs
algorithms
time-complexity
sorting
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1.3k
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3
answers
1
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NIELIT 2017 July Scientist B (CS) - Section B: 10
A queue is implemented using an array such that ENQUEUE and DEQUEUE operations are performed efficiently. Which one of the following statements is CORRECT($n$ refers to ... case time complexity for both operations will be $\Omega(\log n)$.
admin
1.3k
views
admin
asked
Mar 30, 2020
DS
nielit2017july-scientistb-cs
data-structures
queue
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–
1.5k
views
4
answers
0
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NIELIT 2017 July Scientist B (CS) - Section B: 11
Consider the following graph $L$ and find the bridges,if any.No bridge$\{d,e\}$\{c,d\}$\{c,d\}$ and $\{c,f\}$
admin
1.5k
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admin
asked
Mar 30, 2020
Graph Theory
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
bridges
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2.4k
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3
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0
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NIELIT 2017 July Scientist B (CS) - Section B: 12
The following graph has no Euler circuit becauseIt has $7$ vertices.It is even-valent (all vertices have even valence).It is not connected.It does not have a Euler circuit.
admin
2.4k
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admin
asked
Mar 30, 2020
Graph Theory
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
euler-graph
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2.3k
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7
answers
0
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NIELIT 2017 July Scientist B (CS) - Section B: 13
For the graph shown, which of the following paths is a Hamilton circuit?$ABCDCFDEFAEA$AEDCBAF$AEFDCBA$AFCDEBA$
admin
2.3k
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admin
asked
Mar 30, 2020
Graph Theory
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
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8.3k
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4
answers
0
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NIELIT 2017 July Scientist B (CS) - Section B: 14
If $G$ is an undirected planar graph on $n$ vertices with $e$ edges then$e\leq n$e\leq 2n$e\leq 3n$None of the option
admin
8.3k
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admin
asked
Mar 30, 2020
Graph Theory
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
graph-planarity
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3.0k
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2
answers
0
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NIELIT 2017 July Scientist B (CS) - Section B: 15
Choose the most appropriate definition of plane graph.A simple graph which is isomorphic to hamiltonian graph.A graph drawn in a plane in such a way that if the ... that any pair of edges meet only at their end vertices.None of the option.
admin
3.0k
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admin
asked
Mar 30, 2020
Graph Theory
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
graph-planarity
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763
views
3
answers
1
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NIELIT 2017 July Scientist B (CS) - Section B: 16
Which of the following propositions is tautology?$(p\lor q)\to q$p\lor (q\to p)$p\lor (p\to q)$Both (B) and (C)
admin
763
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admin
asked
Mar 30, 2020
Mathematical Logic
nielit2017july-scientistb-cs
mathematical-logic
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2
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1
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NIELIT 2017 July Scientist B (CS) - Section B: 17
The digital multiplexer is basically a combination logic circuit to perform the operationAND-ANDOR-ORAND-OROR-AND
admin
3.8k
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admin
asked
Mar 30, 2020
Digital Logic
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
multiplexer
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1.4k
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2
answers
5
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NIELIT 2017 July Scientist B (CS) - Section B: 18
If $A\oplus B=C$, then which one of the following is true?$A\oplus C=B$B\oplus C=A$A\oplus B\oplus C=0$Both (A) and (B)
admin
1.4k
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admin
asked
Mar 30, 2020
Digital Logic
nielit2017july-scientistb-cs
digital-logic
boolean-algebra
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2
answers
1
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NIELIT 2017 July Scientist B (CS) - Section B: 19
To make the following circuit a tautology ‘?’ marked box should beOR gateAND gateNAND gateEX-OR gate
admin
1.8k
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admin
asked
Mar 30, 2020
Digital Logic
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
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1.0k
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1
answers
1
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NIELIT 2017 July Scientist B (CS) - Section B: 20
In the following gate network which gate is redundant?Gate no.$1$Gate no.$2$Gate no.$3$Gate no.$4$
admin
1.0k
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admin
asked
Mar 30, 2020
Digital Logic
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
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2.5k
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1
answers
1
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NIELIT 2017 July Scientist B (CS) - Section B: 21
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent?NOTORANDXOR
admin
2.5k
views
admin
asked
Mar 30, 2020
Digital Logic
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
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984
views
1
answers
1
votes
NIELIT 2017 July Scientist B (CS) - Section B: 22
What is the average Access Time for a drum rotating at $4000$ revolutions per minute?$2.5$ milliseconds$5.0$ milliseconds$7.5$ milliseconds$4.0$ milliseconds
admin
984
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
disk
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1.1k
views
3
answers
0
votes
NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ?$T1=T2$T1>T2$T1<T2$T1$ is $T2$ plus time taken for one instruction fetch cycle
admin
1.1k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
pipelining
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–
1.4k
views
1
answers
1
votes
NIELIT 2017 July Scientist B (CS) - Section B: 24
How many wires are threaded through the cores in a coincident-current core memory?$2$3$4$6$
admin
1.4k
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admin
asked
Mar 30, 2020
Others
nielit2017july-scientistb-cs
non-gate
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1.1k
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3
answers
1
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NIELIT 2017 July Scientist B (CS) - Section B: 25
Which access method is used for obtaining a record from cassette tape?DirectSequentialRandom Parallel
admin
1.1k
views
admin
asked
Mar 30, 2020
Operating System
nielit2017july-scientistb-cs
operating-system
disk
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–
10.3k
views
2
answers
1
votes
NIELIT 2017 July Scientist B (CS) - Section B: 26
The process of converting the analog sample into discrete form is calledModulationMultiplexingQuantizationSampling
admin
10.3k
views
admin
asked
Mar 30, 2020
Computer Networks
nielit2017july-scientistb-cs
computer-networks
+
–
1.5k
views
4
answers
1
votes
NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor?Static memoryDynamic memoryROMNone of the option
admin
1.5k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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–
1.2k
views
2
answers
1
votes
NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time isSame as the access time.Longer than the access time.Shorter than the access time.Multiple of the access time.
admin
1.2k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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942
views
1
answers
0
votes
NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory hasLower bit density and higher power consumptionHigher bit density and lower power consumptionLower bit density and lower power consumptionNone of the option
admin
942
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
+
–
735
views
1
answers
1
votes
NIELIT 2017 July Scientist B (CS) - Section B: 30
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\times 4$ bits?$13$14$16$17$
admin
735
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
+
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