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Recent questions tagged nielit2017july-scientistb-cs
4
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0
answers
1
NIELIT 2017 July Scientist B (CS) - Section B: 1
What does the following function do for a given Linked List with first node as head? void fun1(struct node* head) { if(head==NULL) return; fun1(head->next); printf("%d",head->data); } Prints all ... lists Prints all nodes of linked list in reverse order Prints alternate nodes of Linked List Prints alternate nodes in reverse order
Lakshman Patel RJIT
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DS
Mar 30, 2020
by
Lakshman Patel RJIT
1.5k
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nielit2017july-scientistb-cs
data-structures
linked-list
0
votes
0
answers
2
NIELIT 2017 July Scientist B (CS) - Section B: 2
Which of the following statements is/are TRUE for an undirected graph? Number of odd degree vertices is even Sum of degrees of all vertices is even P only Q only Both P and Q Neither P nor Q
Lakshman Patel RJIT
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Graph Theory
Mar 30, 2020
by
Lakshman Patel RJIT
902
views
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
degree-of-graph
2
votes
0
answers
3
NIELIT 2017 July Scientist B (CS) - Section B: 3
Consider the following function that takes reference to head of a Doubly Linked List as parameter. Assume that a node of doubly linked list has previous pointer as $\textit{prev}$ and next pointer as $\textit{next}$. ... $6 \leftrightarrow 5 \leftrightarrow 4 \leftrightarrow 3 \leftrightarrow 1 \leftrightarrow 2$
Lakshman Patel RJIT
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DS
Mar 30, 2020
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Lakshman Patel RJIT
934
views
nielit2017july-scientistb-cs
data-structures
linked-list
1
vote
3
answers
4
NIELIT 2017 July Scientist B (CS) - Section B: 4
Let $A$ be a square matrix of size $n\times n$. Consider the following program. What is the expected output? C=100 for i=1 to n do for j=1 to n do { Temp=A[i][j]+C A[i][j]=A[j][i] A[j][i]=Temp-C } ... itself. Transpose of matrix $A$. Adding $100$ to the upper diagonal elements and subtracting $100$ from diagonal elements of $A$. None of the option.
Lakshman Patel RJIT
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in
DS
Mar 30, 2020
by
Lakshman Patel RJIT
734
views
nielit2017july-scientistb-cs
data-structures
array
1
vote
2
answers
5
NIELIT 2017 July Scientist B (CS) - Section B: 5
Following is C like Pseudo code of a function that takes a number as an argument, and uses a stack S to do processing. void fun(int n) { Stack S;//Say it creates an empty stack S while(n>0) { // This line pushes the value of ... . Prints binary representation of $n$. Prints the value of $\log n$. Prints the value of $\log n$ in reverse order.
Lakshman Patel RJIT
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Programming
Mar 30, 2020
by
Lakshman Patel RJIT
1.8k
views
nielit2017july-scientistb-cs
programming-in-c
2
votes
2
answers
6
NIELIT 2017 July Scientist B (CS) - Section B: 6
Assume that the operators $+,-,\times$ are left associative and $\wedge$ is right associative. The order of precedence(from highest to lowest) is $\wedge,\times, +,-$ ... $abc\times+de\wedge f\wedge-$ $ab+c\times d-e\wedge f\wedge $ $-+a\times bc\wedge\wedge def$
Lakshman Patel RJIT
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in
DS
Mar 30, 2020
by
Lakshman Patel RJIT
819
views
nielit2017july-scientistb-cs
data-structures
stack
infix-prefix
2
votes
2
answers
7
NIELIT 2017 July Scientist B (CS) - Section B: 7
A balance factor in AVL tree is used to check what rotation to make if all child nodes are at same level when the last rotation occurred if the tree is unbalanced
Lakshman Patel RJIT
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in
DS
Mar 30, 2020
by
Lakshman Patel RJIT
3.9k
views
nielit2017july-scientistb-cs
data-structures
avl-tree
1
vote
2
answers
8
NIELIT 2017 July Scientist B (CS) - Section B: 8
A priority queue is implemented as a Max-Heap. Initially, it has $5$ elements. The level-order traversal of the heap is: $10,8,5,3,2$. Two new elements $1$ and $7$ are inserted into the heap in that order. The level-order traversal of the heap after the insertion of the elements is $10,8,7,3,2,1,5$ $10,8,7,2,3,1,5$ $10,8,7,1,2,3,5$ $10,8,7,5,3,2,1$
Lakshman Patel RJIT
asked
in
DS
Mar 30, 2020
by
Lakshman Patel RJIT
552
views
nielit2017july-scientistb-cs
data-structures
priority-queue
heap
2
votes
1
answer
9
NIELIT 2017 July Scientist B (CS) - Section B: 9
The worst case running times of Insertion sort, Merge sort and Quick sort, respectively, are $\Theta(n \log n),\Theta(n \log n) \text{ and } \Theta(n^2)$ $\Theta(n^2),\Theta(n^2)\text{ and } \Theta(n \log n)$ $\Theta(n^2), \Theta(n \log n)\text{ and } \Theta(n \log n)$ $\Theta(n^2),\Theta(n\log n) \text{ and } \Theta(n^2)$
Lakshman Patel RJIT
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in
Algorithms
Mar 30, 2020
by
Lakshman Patel RJIT
559
views
nielit2017july-scientistb-cs
algorithms
time-complexity
0
votes
3
answers
10
NIELIT 2017 July Scientist B (CS) - Section B: 10
A queue is implemented using an array such that ENQUEUE and DEQUEUE operations are performed efficiently. Which one of the following statements is CORRECT($n$ ... operations will be $\Omega(n)$. Worst case time complexity for both operations will be $\Omega(\log n)$.
Lakshman Patel RJIT
asked
in
DS
Mar 30, 2020
by
Lakshman Patel RJIT
765
views
nielit2017july-scientistb-cs
data-structures
queue
0
votes
4
answers
11
NIELIT 2017 July Scientist B (CS) - Section B: 11
Consider the following graph $L$ and find the bridges,if any. No bridge $\{d,e\}$ $\{c,d\}$ $\{c,d\}$ and $\{c,f\}$
Lakshman Patel RJIT
asked
in
Graph Theory
Mar 30, 2020
by
Lakshman Patel RJIT
836
views
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
bridges
0
votes
3
answers
12
NIELIT 2017 July Scientist B (CS) - Section B: 12
The following graph has no Euler circuit because It has $7$ vertices. It is even-valent (all vertices have even valence). It is not connected. It does not have a Euler circuit.
Lakshman Patel RJIT
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in
Graph Theory
Mar 30, 2020
by
Lakshman Patel RJIT
1.6k
views
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
euler-graph
0
votes
7
answers
13
NIELIT 2017 July Scientist B (CS) - Section B: 13
For the graph shown, which of the following paths is a Hamilton circuit? $ABCDCFDEFAEA$ $AEDCBAF$ $AEFDCBA$ $AFCDEBA$
Lakshman Patel RJIT
asked
in
Graph Theory
Mar 30, 2020
by
Lakshman Patel RJIT
1.5k
views
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
0
votes
4
answers
14
NIELIT 2017 July Scientist B (CS) - Section B: 14
If $G$ is an undirected planar graph on $n$ vertices with $e$ edges then $e\leq n$ $e\leq 2n$ $e\leq 3n$ None of the option
Lakshman Patel RJIT
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in
Graph Theory
Mar 30, 2020
by
Lakshman Patel RJIT
6.9k
views
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
graph-planarity
0
votes
2
answers
15
NIELIT 2017 July Scientist B (CS) - Section B: 15
Choose the most appropriate definition of plane graph. A simple graph which is isomorphic to hamiltonian graph. A graph drawn in a plane in such a way that if the vertex set of graph can be partitioned into two non-empty disjoint subset $X$ and ... in a plane in such a way that any pair of edges meet only at their end vertices. None of the option.
Lakshman Patel RJIT
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in
Graph Theory
Mar 30, 2020
by
Lakshman Patel RJIT
2.2k
views
nielit2017july-scientistb-cs
discrete-mathematics
graph-theory
graph-planarity
1
vote
3
answers
16
NIELIT 2017 July Scientist B (CS) - Section B: 16
Which of the following propositions is tautology? $(p\lor q)\to q$ $p\lor (q\to p)$ $p\lor (p\to q)$ Both (B) and (C)
Lakshman Patel RJIT
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in
Mathematical Logic
Mar 30, 2020
by
Lakshman Patel RJIT
482
views
nielit2017july-scientistb-cs
mathematical-logic
0
votes
2
answers
17
NIELIT 2017 July Scientist B (CS) - Section B: 17
The digital multiplexer is basically a combination logic circuit to perform the operation AND-AND OR-OR AND-OR OR-AND
Lakshman Patel RJIT
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in
Digital Logic
Mar 30, 2020
by
Lakshman Patel RJIT
2.2k
views
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
multiplexer
3
votes
2
answers
18
NIELIT 2017 July Scientist B (CS) - Section B: 18
If $A\oplus B=C$, then which one of the following is true? $A\oplus C=B$ $B\oplus C=A$ $A\oplus B\oplus C=0$ Both (A) and (B)
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 30, 2020
by
Lakshman Patel RJIT
725
views
nielit2017july-scientistb-cs
digital-logic
boolean-algebra
1
vote
2
answers
19
NIELIT 2017 July Scientist B (CS) - Section B: 19
To make the following circuit a tautology ‘?’ marked box should be OR gate AND gate NAND gate EX-OR gate
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 30, 2020
by
Lakshman Patel RJIT
735
views
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
0
votes
1
answer
20
NIELIT 2017 July Scientist B (CS) - Section B: 20
In the following gate network which gate is redundant? Gate no.$1$ Gate no.$2$ Gate no.$3$ Gate no.$4$
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 30, 2020
by
Lakshman Patel RJIT
482
views
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
0
votes
1
answer
21
NIELIT 2017 July Scientist B (CS) - Section B: 21
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent? NOT OR AND XOR
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 30, 2020
by
Lakshman Patel RJIT
1.4k
views
nielit2017july-scientistb-cs
digital-logic
combinational-circuit
0
votes
1
answer
22
NIELIT 2017 July Scientist B (CS) - Section B: 22
What is the average Access Time for a drum rotating at $4000$ revolutions per minute? $2.5$ milliseconds $5.0$ milliseconds $7.5$ milliseconds $4.0$ milliseconds
Lakshman Patel RJIT
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in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
461
views
nielit2017july-scientistb-cs
co-and-architecture
disk
0
votes
3
answers
23
NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
625
views
nielit2017july-scientistb-cs
co-and-architecture
pipelining
1
vote
1
answer
24
NIELIT 2017 July Scientist B (CS) - Section B: 24
How many wires are threaded through the cores in a coincident-current core memory? $2$ $3$ $4$ $6$
Lakshman Patel RJIT
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in
Others
Mar 30, 2020
by
Lakshman Patel RJIT
646
views
nielit2017july-scientistb-cs
non-gate
1
vote
3
answers
25
NIELIT 2017 July Scientist B (CS) - Section B: 25
Which access method is used for obtaining a record from cassette tape? Direct Sequential Random Parallel
Lakshman Patel RJIT
asked
in
Operating System
Mar 30, 2020
by
Lakshman Patel RJIT
440
views
nielit2017july-scientistb-cs
operating-system
disk
1
vote
2
answers
26
NIELIT 2017 July Scientist B (CS) - Section B: 26
The process of converting the analog sample into discrete form is called Modulation Multiplexing Quantization Sampling
Lakshman Patel RJIT
asked
in
Computer Networks
Mar 30, 2020
by
Lakshman Patel RJIT
8.1k
views
nielit2017july-scientistb-cs
computer-networks
1
vote
4
answers
27
NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor? Static memory Dynamic memory ROM None of the option
Lakshman Patel RJIT
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in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
898
views
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
0
votes
2
answers
28
NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time is Same as the access time. Longer than the access time. Shorter than the access time. Multiple of the access time.
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
467
views
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
0
votes
1
answer
29
NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory has Lower bit density and higher power consumption Higher bit density and lower power consumption Lower bit density and lower power consumption None of the option
Lakshman Patel RJIT
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
450
views
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
0
votes
1
answer
30
NIELIT 2017 July Scientist B (CS) - Section B: 30
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\times 4$ bits? $13$ $14$ $16$ $17$
Lakshman Patel RJIT
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in
CO and Architecture
Mar 30, 2020
by
Lakshman Patel RJIT
365
views
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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