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Recent questions tagged pipelining

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pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)

Veeresh Badiger asked in CO and Architecture Mar 5

by Veeresh Badiger

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2

pipeline
6. A processor X1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. ... , the speed up (rounded off to two decimal places) obtained by X2 over X1 in executing P is ?. (GATE CSE 2022)

Veeresh Badiger asked in CO and Architecture Mar 5

by Veeresh Badiger

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2 votes

3 answers

3

GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third stages, respectively. Assume that there is no other ... instruction is fetched every cycle. The total execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$

admin asked in CO and Architecture Feb 15

by admin

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4

Operand forwarding Made Easy Question
Consider 4-stage (IF, ID, EX, WB) pipeline used to execute the following code. All instructions are spending are spending one cycle on all the stages but ALU instructions are spending 3 cycles on 3rd stage. I1: LOAD R0, ... Number of cycles are saved using operand forwarding over without operand forwarding is? Can someone please explain by drawing the diagram?

Chaitanya Kale asked in CO and Architecture Jan 30

by Chaitanya Kale

188 views

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1 answer

5

PERSONAL DOUBT [PIPELINING]
So I know pipelining has 5 stages: IF, ID, EX, MA, WB. Now the question is if I have a program of few instruction which has both ALU operation and LOAD/store operation in any sequence. So tell me among the 5 stages how many stages will be reqiured for ALU and how many for LOAD/STORE.

DAWID15 asked in CO and Architecture Dec 26, 2022

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6

Calcutta University Question Paper
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MALS 0 1 2 3 4 S1 A B A B S2 A A S3 B AB A

sikkaBrown asked in CO and Architecture Dec 18, 2022

95 views

1 vote

3 answers

7

CO and Arcitecture | RISC | Instruction pipelining
MSQ Which among the following statements is/are TRUE for a pipelined RISC computer. PC is usually incremented during Instruction Cycle (IF,ID) PC may be incremented during Execution Cycle (EX,MA,WB) Filling the Accumulator ... during the Instruction Cycle (IF,ID) All non-register memory fetching operations are done in Load instructions only.

Souvik33 asked in CO and Architecture Dec 16, 2022

230 views

1 vote

1 answer

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Computer Organization and architecture
Consider a hypothetical processor which supports expand opcode technique. A 32 bit instruction is place in 256MW memory. If there exist 10, one address instruction then how many zero-address instruction are possible.

iabhay.gupta asked in CO and Architecture Dec 11, 2022

by iabhay.gupta

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9

University Assignment
𝑙𝑜𝑜𝑝: 1. 𝐴𝐷𝐷𝐼 𝑅2, 𝑅2, #1 2. 𝐿𝐷 𝑅4, 0(𝑅3) 3. 𝐿𝐷 𝑅5, 4(𝑅3) 4. 𝐴𝐷𝐷 𝑅6, 𝑅4, 𝑅5 5. 𝑀𝑈𝐿 𝑅4, 𝑅6, 𝑅7 6. 𝑆𝑈𝐵𝐼 𝑅3, 𝑅3, #8 7. 𝐵𝑁𝐸𝑍 𝑅2, 𝑙𝑜𝑜𝑝 8. 𝐴𝐷𝐷 𝑅11, 𝑅12, 𝑅13 Question: Assume a 5-stage pipeline (IF ID EX MEM WB) ... All stages take 1 cycle. Again, the loop takes one iteration to complete. Which dependencies from part (a) cause stalls? How many cycles does the loop take to execute?

lalitver10 asked in CO and Architecture Nov 14, 2022

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pipelining with branch instructions
ADD R1,R2,R3 SUB R2,R1,R7 BNEQZ R5,L1 MUL R8,R9,R3 DIV R6,R8,R7 L1:- LOAD R4, 2(R6) SUB R10,R4,R11 for the above sequence of instructions draw time and space diagram to find out total number of clock cycles required to complete execution without operand forwarding and if branch is not taken

anas_2908 asked in CO and Architecture Oct 21, 2022

229 views

0 votes

1 answer

11

[email protected] 2022
Answer 1.03

Amit Mehta asked in CO and Architecture Oct 21, 2022

181 views

0 votes

2 answers

12

[email protected] 2022 Test Series
Answer 1.18

Amit Mehta asked in CO and Architecture Oct 21, 2022

132 views

0 votes

0 answers

13

[email protected] 2022
Answer 1.125

Amit Mehta asked in CO and Architecture Oct 21, 2022

84 views

0 votes

0 answers

14

[email protected] 2022 Test Series
Answer (A)

Amit Mehta asked in CO and Architecture Oct 21, 2022

90 views

0 votes

1 answer

15

Madeeasy Test Series 2023
Answer: 1.098

Amit Mehta asked in CO and Architecture Oct 20, 2022

143 views

0 votes

0 answers

16

[email protected] Test Series 2022
Answer 3.12

Amit Mehta asked in CO and Architecture Oct 20, 2022

142 views

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Recent questions tagged pipelining