Recent questions tagged pipelining

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1

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

asked May 23 in CO and Architecture by Hirak Active (3.4k points) | 83 views

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1 answer

2

ISI2018-PCB-CS8
Consider a $5$ ... $(in\ ns)$ needed to execute the program.

asked May 12 in Operating System by akash.dinkar12 Boss (41.6k points) | 77 views

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3

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18 in CO and Architecture by Doraemon (471 points) | 49 views

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1 answer

4

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

asked Mar 8 in CO and Architecture by s_dr_13 (155 points) | 92 views

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1 answer

5

Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

asked Feb 18 in CO and Architecture by DIYA BASU (233 points) | 74 views

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6

Self Doubt
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK

asked Feb 18 in CO and Architecture by DIYA BASU (233 points) | 42 views

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7

Made easy test series pipelining
Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4? A. 1.33 B. 1.76 C. 1.14 D. 1.66

asked Jan 23 in CO and Architecture by Ram Swaroop Active (4.2k points) | 207 views

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8

Instruction Pipeline
Consider an instruction pipeline with five stages , it allows overlapping of all instructions except branch type. Let there are 20% branch instructions and pipeline is operated with 800 megahertz. 1) what is the speedup? 2) what is average instruction time. 3) what is the time taken for 10 million instructions. 4) what is the throughput.

asked Jan 19 in CO and Architecture by Nandkishor3939 Active (1.3k points) | 169 views

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9

Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.

asked Jan 19 in CO and Architecture by Nandkishor3939 Active (1.3k points) | 95 views

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10

PIPELINING
#PLEASEEXPLAINIAMNOTGETTING. Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2, $4, $2 ADD $1, $3, $5 SW $2, 20($4) ADD $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

asked Jan 16 in CO and Architecture by Himanshu Kashyap Junior (529 points) | 41 views

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1 answer

11

MadeEasy Test Series 2019: CO & Architecture - Pipelining
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)

asked Jan 16 in CO and Architecture by Satbir Boss (19.1k points) | 121 views

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2 answers

12

Madeeasy- Types of Dependencies
Please clarify along with the names.

asked Jan 9 in CO and Architecture by Markzuck Junior (655 points) | 81 views

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13

ME TEST SERIES
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. If p is a the probability of an instruction being a branch instruction then the value of p such that speed up is atleast 3 is ________. (Upto 2 decimal places)

asked Jan 9 in CO and Architecture by himgta Active (3.6k points) | 194 views

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14

How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)

asked Jan 9 in CO and Architecture by Raj Singh 1 (287 points) | 64 views

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1 answer

15

Data forwarding in pipelining
Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR

asked Jan 2 in CO and Architecture by Abhilash Mishra (91 points) | 142 views

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1 answer

16

Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.

asked Jan 1 in CO and Architecture by Alina (9 points) | 171 views

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1 answer

17

Pipelining
Why pipelining cannot operate at its maximum theoretical speed? Maximum theoretical is when we say that it takes same time to process an instruction in pipeline and non pipeline circuit. So why pipelining cannot operate at its maximum theoretical speed?

asked Dec 31, 2018 in CO and Architecture by Alina (9 points) | 41 views

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18

Avoiding pipeline Hazards
Please Confirm.

asked Dec 27, 2018 in CO and Architecture by smsubham Loyal (9.2k points) | 104 views

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19

Self doubt
If the time taken by a task to get completed is same in the pipeline and non pipeline circuits, then how the time taken to complete the task in non pipeline = k* time taken to complete the task in pipeline where k is no. of segments in the pipeline?

asked Dec 27, 2018 in CO and Architecture by Nivedita Singh (29 points) | 39 views

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1 answer

20

ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages ... of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825

asked Dec 25, 2018 in CO and Architecture by newdreamz a1-z0 Active (1.6k points) | 127 views

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21

MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)

asked Dec 25, 2018 in CO and Architecture by Markzuck Junior (655 points) | 177 views

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22

stage delays doubt in pipelining
if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last stage. each register delay is 1ns. How the time taken by a NON-PIPELINED implementation is calculated for n no. of instructions? and what is the speed up here?

asked Dec 22, 2018 in CO and Architecture by Ashwani Yadav Active (1.2k points) | 163 views

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23

Calculate speed up ratio of pipeline
Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.

asked Dec 21, 2018 in CO and Architecture by Alina (9 points) | 867 views

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24

gatebook test
Suppose the functions F and G can be computed in 8 and 3 nanoseconds by functional units UF and UG, respectively. Given three instances of UF and three instances of UG, it is required to implement the computation F(G(Xi)) for 1 ≤ i ≤ 13. A control Unit selects next task/s ... this computation is ( in nanoseconds): (A) 28 (B) 33 (C) 43 (D) 49 my answer is 43 but gatebook answer is 49.

asked Dec 18, 2018 in CO and Architecture by sushmita Boss (16.8k points) | 98 views

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25

Pipeline
A pipelined Processor contains 5 instructions stages of execution times 120ns, 160ns, 105 ns, 135ns and 155ns with a register delay 10ns on each stage. What is the percentage of performance increased with 1000 instructions instead of 10 instructions

asked Dec 18, 2018 in CO and Architecture by aditi19 Active (4.9k points) | 172 views

+2 votes

2 answers

26

MadeEasy Subject Test 2019: CO & Architecture - Pipelining
Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?

asked Dec 18, 2018 in CO and Architecture by jatin khachane 1 Loyal (7k points) | 459 views

+1 vote

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27

https://gateoverflow.in/753/gate2001-12?show=279851#c279851
doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851 In instruction I3 how is it getting the value of r2 which is computed in I1 instruction?? Can memory access stage read the value of updated register values of write back stage?? please resolve my doubt.

asked Dec 18, 2018 in CO and Architecture by sushmita Boss (16.8k points) | 78 views

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28

general doubt on pipelining
we do forwarding from WB stage to EX or from WB to MEM stage??

asked Dec 18, 2018 in CO and Architecture by sushmita Boss (16.8k points) | 67 views

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1 answer

29

MadeEasy Test Series: CO & Architecture - Pipelining
A system employs $10$ stage instruction pipeline in which $5$% instruction results in data dependency, $10$% instruction results in control dependency, $2$% instructions results in structural dependency. $10$% instructions are exposed ... dependency are $3$ clocks and $2$ clocks respectively. The average instruction time is _______ [in cycles]

asked Dec 16, 2018 in CO and Architecture by zeeshanmohnavi Junior (897 points) | 345 views

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1 answer

30

Branch Target Address
In a normal 5-stage pipeline, when is the branch target address available? There are some sources which say that the address is available after the MEM stage, but go on to say that it can be found out after the ID stage if we put in an extra ... in which they assumed that the address is available after the 4th stage. Is that the approach to be followed for all the questions?

asked Dec 11, 2018 in CO and Architecture by goxul Loyal (6.3k points) | 61 views

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