Recent questions tagged pipelining

0 votes

0 answers

1

William Stallings - Computer Organization and Architecture D
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . . ... from the use of the cache. Assume an LRU policy for block replacement. Show the state of cache at the end.

lucifer069 asked in CO and Architecture Sep 16

47 views

0 votes

2 answers

2

UGCNET-Dec2019-II: 9
A non-pipelined system takes $\text{30ns}$ to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of $\text{10ns}$. Determine the speed up of the pipeline for $100$ tasks. $3$ $4$ $3.91$ $2.91$

soujanyareddy13 asked in Others May 12

by soujanyareddy13

148 views

8 votes

3 answers

3

GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________

Arjun asked in CO and Architecture Feb 18

by Arjun

2.9k views

2 votes

2 answers

4

GATE CSE 2021 Set 1 | Question: 53
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.

Arjun asked in CO and Architecture Feb 18

by Arjun

1k views

0 votes

2 answers

5

UGCNET-Oct2020-II: 7
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

565 views

0 votes

1 answer

6

UGCNET-Oct2020-II: 43
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

403 views

0 votes

2 answers

7

NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 18
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

412 views

2 votes

3 answers

8

NIELIT 2016 DEC Scientist B (CS) - Section B: 23
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

829 views

0 votes

3 answers

9

NIELIT 2017 July Scientist B (CS) - Section B: 23
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

449 views

1 vote

5 answers

10

NIELIT 2017 DEC Scientist B - Section B: 13
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage ... What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

1.9k views

0 votes

3 answers

11

NIELIT 2017 DEC Scientist B - Section B: 14
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

830 views

15 votes

3 answers

12

GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.

Arjun asked in CO and Architecture Feb 12, 2020

by Arjun

7k views

6 votes

1 answer

13

ISRO2020-6
A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported $\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra to Rb and store the result in Rr} \end{array}$ ... $R0,R1$ and $R2$ and contents of these registers must not be modified. $5$ $6$ $7$ $8$

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

1.4k views

4 votes

4 answers

14

ISRO2020-7
Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

3.1k views

0 votes

0 answers

15

Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 11 (Page No. 430)
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and ... instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.

Lakshman Patel RJIT asked in CO and Architecture Oct 28, 2019

by Lakshman Patel RJIT

418 views

0 votes

4 answers

16

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

Lakshman Patel RJIT asked in CO and Architecture Oct 23, 2019

by Lakshman Patel RJIT

702 views

1 vote

1 answer

17

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

Hirak asked in CO and Architecture May 23, 2019

by Hirak

285 views

1 vote

2 answers

18

ISI2018-PCB-CS8
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.

akash.dinkar12 asked in Operating System May 12, 2019

by akash.dinkar12

662 views

Page:

1
2
3
4
5
6
...
13
next »

Follow @gateoverflow

GATE Overflow

Recent questions tagged pipelining

Search GATE Overflow