# Recent questions tagged pipelining

1
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
2
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
3
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None
1 vote
4
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$
5
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle
1 vote
6
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage for clock skew and set up. What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
7
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
8
A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported $\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra to Rb and store the result in Rr} \end{array}$ ... $X,Y,Z$ are initially available in registers $R0,R1$ and $R2$ and contents of these registers must not be modified. $5$ $6$ $7$ $8$
9
Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$
10
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and the PC advanced. Each instruction occupies exactly ... stage and the first instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.
11
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?
1 vote
12
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?
13
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.
14
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB
1 vote
15
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE
1 vote
16
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .
1 vote
17
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK
18
Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4? A. 1.33 B. 1.76 C. 1.14 D. 1.66
19
Consider an instruction pipeline with five stages , it allows overlapping of all instructions except branch type. Let there are 20% branch instructions and pipeline is operated with 800 megahertz. 1) what is the speedup? 2) what is average instruction time. 3) what is the time taken for 10 million instructions. 4) what is the throughput.
1 vote
Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2,$4, $2 ADD$1, $3,$5 SW $2, 20($4) ADD $1,$1, \$4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?