# Recent questions tagged pipelining

1
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup}$ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
2
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
3
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
4
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
5
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None
6
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$
7
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle
1 vote
8
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage for clock skew and set up. What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
9
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
10
A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported $\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra to Rb and store the result in Rr} \end{array}$ ... $X,Y,Z$ are initially available in registers $R0,R1$ and $R2$ and contents of these registers must not be modified. $5$ $6$ $7$ $8$
11
Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$
12
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and the PC advanced. Each instruction occupies exactly ... stage and the first instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.
13
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?
1 vote
14
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?
1 vote
15
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.