Recent questions tagged pipelining

0 votes

1 answer

1

Pipeline
Give answer for question no. 12 please! provide detailed answer.

asked 3 days ago in CO & Architecture by learner_geek Loyal (3k points) | 36 views

+1 vote

1 answer

2

Pipelining Speedup
Consider a non-pipelined processor design which has a cycle time of 15ns and average CPI of 1.6. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 3ns is______________? 5 6 10 7

asked 5 days ago in CO & Architecture by akb1115 Active (1.8k points) | 47 views

+1 vote

0 answers

3

Pipeline
Suppose there is unpipelined processor with cycle time 30 ns,which is evenly divided into 5 pipeline stages. The total latch latency of the pipeline will be____________ns

asked Oct 9 in CO & Architecture by srestha Veteran (65k points) | 26 views

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0 answers

4

to solve speedup
The only instruction in the 5-stage pipelined MIPS that needs all 5 stages is Load. It has been suggested to design a 4-stage pipeline where the 4th stage will allow either a memory (read or write) operation, or a Register File write. ... the two pipelines will have the same cycle time, what is the speedup of the 5-stage pipeline over the 4-stage one?

asked Sep 29 in CO & Architecture by Howard.xu0527 (33 points) | 51 views

0 votes

0 answers

5

solve structural hazard CPI
A 5-stage pipeline has a Register File that can execute either a Read operation (of 1 or 2 registers) or a Write operation (into only one register), but not both, during every clock cycle. The instruction mix that ... a Register File capable of performing two reads and one write every cycle over the pipeline with the limited Register file?

asked Sep 29 in CO & Architecture by Howard.xu0527 (33 points) | 34 views

0 votes

2 answers

6

What is the maximum speedup achieved in new pipeline system?

asked Sep 29 in CO & Architecture by sunil sarode (389 points) | 87 views

0 votes

0 answers

7

Hazard in Pipeline
I know this question is already asked, But here my doubt is different, I have seen many people calculating the RAW hazard without seeing the no of stages in the pipeline which is not correct. In the above question If we see clearly by keeping ... last line also it is written that:- The SW is no problem at all, since it reads $2 after the SUB ﬁnishes.

asked Sep 28 in CO & Architecture by Shubhanshu Boss (8.9k points) | 35 views

0 votes

1 answer

8

Find average CPI of non-pipeline CPU(assume ideal case for pipelining)?

asked Sep 28 in CO & Architecture by sunil sarode (389 points) | 44 views

0 votes

0 answers

9

How Structural Hazard is possible for following ?

asked Sep 28 in CO & Architecture by sunil sarode (389 points) | 33 views

0 votes

0 answers

10

RAW hazard
I have gone through several links related to raw harazd.. Some are saying, we consider RAW hazard between adjacent instruction only..EX http://gateoverflow.in/17729/raw-dependencies http://gateoverflow.in/116280/made-easy-co http:// ... //gateoverflow.in/753/gate2001-12 Iam confuse, in RAW dependency should we look for non adjacent instruction also ??

asked Sep 28 in CO & Architecture by stblue Boss (6.4k points) | 33 views

0 votes

1 answer

11

Pipeline Architecture (CSO)
Generally there are two formulas for finding out time taken by n jobs in a pipeline, time for processing n jobs = time taken by 1 job + (n-1)*(time of the largest stage) - (1) here n is the no. of jobs/instructions needed ... Tp = Clock cycle time Both give different timings / values. So which one should be used when??? Please help... Thanks

asked Sep 27 in CO & Architecture by abhijeetbzu (25 points) | 48 views

+2 votes

1 answer

12

Find out the throughput of pipelining

asked Aug 13 in CO & Architecture by hem chandra joshi Loyal (2.6k points) | 124 views

+2 votes

1 answer

13

Self Doubt In CO
Consider an instruction which has a speed up factor 12 while operating with a 70% efficiency. What could be the number of stages in the pipeline? What will be its answer 17 or 18? And why?

asked Jul 20 in CO & Architecture by Shubhanshu Boss (8.9k points) | 73 views

+1 vote

0 answers

14

doubt in COA
Will a RAW hazard always cause the pipeline to stall ??? NO right ? Here though we have RAW hazard it doesnot need to stall the pipeline .. right ???

asked Jul 18 in CO & Architecture by Vicky rix Loyal (4.9k points) | 34 views

+1 vote

1 answer

15

CO , STRUCTURAL HAZARD
Consider a hypothetical system with 4 stage pipelining and 2 instructions. IF , ID, EX and WB are the stages.if IF ID EX take 1 cycle each in both the instructions.WB stage takes 2 cycles in I1 and 1 cycle in I2. ... the 5th cycle as both of them perform write operations on different registers ? Does it contain structural dependency in WB stage ?

asked Jul 18 in CO & Architecture by Saswat Swarup Junior (627 points) | 57 views

+1 vote

1 answer

16

COA problem in pipelining
Consider a 4 stage pipeline with stages named S1,S2,S3,S4. Let I1,I2,I3,I4 be 4 instructions and the number of clock-cycles needed by each instruction in each stage is given below. The number of clock-cycles needed to complete the instruction cycle of the 4 instructions is ___.

asked Jul 16 in CO & Architecture by Vicky rix Loyal (4.9k points) | 106 views

+3 votes

2 answers

17

Pipeline hazards
If, a multicycle,pipelined processor has ‘N’ pipeline stages, then structural hazards can be avoided completely if at least ‘N’ registers are available. Is this true or false?

asked Jul 16 in CO & Architecture by shraddha priya Active (2.1k points) | 122 views

+2 votes

0 answers

18

doubt in coa
is it 5 or 4 ..?? some places i am finding it as 4 (number of cycles) and in some places it is given as 5(number of slots)..please confirm

asked Jul 15 in CO & Architecture by Vicky rix Loyal (4.9k points) | 32 views

+1 vote

1 answer

19

Number of stall cycles in case of branch misprediction

asked Jul 9 in CO & Architecture by GateAspirant999 Active (2.1k points) | 46 views

+2 votes

0 answers

20

Dealing with ALU-ALU forwarding

asked Jun 26 in CO & Architecture by GateAspirant999 Active (2.1k points) | 39 views

0 votes

2 answers

21

Hazard in Pipelining
Consider the Program segment I1: r0 <- r1 + r2; I2: r2 <- r0 * r3; I3: r0 <- r2 / r0; I4: r3 <- r2 * r0; I5: M[x] <- r3; Q1> Calculate the number of - 1. Read after write hazard 2. Write after Read hazard 3. Write after Write hazard. Q2> which of these hazards happen between the two adjacents instructions.

asked Apr 30 in CO & Architecture by Shubhanshu Boss (8.9k points) | 85 views

0 votes

1 answer

22

ISI-JRF
A machine M has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses: F-stage - instruction fetch (9 ns), D-stage - instruction decode and register fetch (3 ns), X-stage - ... where every 3rd instruction needs a 1-cycle stall before the X-stage. Calculate the CPU time in seconds for completing P.

asked Apr 20 in CO & Architecture by kauray (325 points) | 76 views

+7 votes

5 answers

23

GATE2017-1-50
Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns ... speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________ .

asked Feb 14 in CO & Architecture by khushtak Boss (7.6k points) | 1.8k views

+1 vote

1 answer

24

#GATE2017_1
Consider a five stage pipeline having stages IF,ID,OF,EX and WB having stage delays 5,6,14,20 and 8 ns. Buffer delay is 2 ns.(say this is pipeline design 1). Now in this design, if we break the EX stage into 2 stages having delays ... ns(say this is design 2). What is the speedup we can get by using design 2 over design 1 for executing 20 instructions ?

asked Feb 13 in CO & Architecture by Vivek Jain Junior (799 points) | 301 views

+1 vote

1 answer

25

Mock Test
The answer given is D) Why is option 3 and 4 correct ? In 4) if there is a branch instruction , it can lead to stalls ,so how will it improve the execution ?

asked Feb 5 in CO & Architecture by Harsh181996 Loyal (3.6k points) | 62 views

+2 votes

1 answer

26

COA pipeline doubt
I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline??? II) In a 4 stage pipeline processor, if each stage takes 2,3,4,5 cycles respectively then ... imstructions and branch address is available in 3rd stage then what should be branch pelanty??(In both the implementations mentioned above)

asked Feb 5 in CO & Architecture by Rahul Jain25 Veteran (12.2k points) | 160 views

+1 vote

1 answer

27

Pipeline
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th ... ,R_{4}$ What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.

asked Feb 4 in CO & Architecture by srestha Veteran (65k points) | 209 views

0 votes

1 answer

28

Pipeline: Calculate average instruction execution time

asked Jan 30 in CO & Architecture by sh!va Veteran (30.2k points) | 182 views

+5 votes

0 answers

29

Doubts in PIpelining
1. In case of no data forwarding can we use split phase. 2. Should we have to consider data forwarding, According to options? 3. Where we can use split phase??( I know about WB-ID and EX-ID) @Pc @Arjun Sir Please answer..

asked Jan 30 in CO & Architecture by vaishali jhalani Boss (6.5k points) | 251 views

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