Recent questions tagged pipelining

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1

Operand Forwarding
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage takes one cycle. How many instructions must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6

asked 4 days ago in CO & Architecture by Na462 Loyal (6.4k points) | 20 views

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2

Is superscalar operations in pipelining part of gate syllabus

asked Oct 4 in CO & Architecture by bts1jimin (87 points) | 9 views

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3

Branch prediction in pipelining part of syllabhs?

asked Oct 3 in CO & Architecture by bts1jimin (87 points) | 19 views

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4

Pipeline performance reduced if different stages have different execution delays

asked Oct 2 in CO & Architecture by Harsh Kumar Junior (769 points) | 15 views

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5

Minimum clock cycle

asked Sep 24 in CO & Architecture by Na462 Loyal (6.4k points) | 54 views

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6

#CO pipeline doubt
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute the following loop? For (i=1 to 2){I1; I2; ... stage, the current instruction(I4) cannot execute a given stage P.S.- Refer here- https://gateoverflow.in/244642/%23co-gate-2009-self-doubt

asked Sep 21 in CO & Architecture by iarnav Loyal (8.6k points) | 38 views

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7

#CO Gate 2009 Self Doubt.
Original question- https://gateoverflow.in/1314/gate2009-28 In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stage? In this question if we take the above approach, we will get different ... , Refer this GATE 2004-IT question- https://gateoverflow.in/3690/gate2004-it-47 in this we are doing as the above approach.

asked Sep 19 in CO & Architecture by iarnav Loyal (8.6k points) | 23 views

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8

Self Doubt : Pipe lining
Given 100 instructions executed on a 5 stage pipeline . probability (p) that an instruction is branch is p. Branch penalty 4.Assuming that each stage of pipeline takes 1 cycle.Calculate total execution time. My query is since first instruction will take 5 clk so how to calculate ? is 5+ 99[(1-p)*1 + p*4] the correct approach ?

asked Sep 8 in CO & Architecture by Shiv Gaur Active (1.4k points) | 28 views

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9

Operand Forwarding Doubt
I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??

asked Sep 3 in CO & Architecture by Na462 Loyal (6.4k points) | 29 views

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10

Pipeline Doubt
Its a snapshot from hamacher. According to me there should be stall of 2 cycles why 3 ?? Because after Write stage the data will be available in register file so why extra stall in 6th clock cycle ?

asked Sep 3 in CO & Architecture by Na462 Loyal (6.4k points) | 40 views

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11

COA -INSTRUCTION PIPELINE
Consider a 4 stage pipeline:fetch-IF(2cycle), decode& read -ID(1 cycle) execute-Ex(4 cycle for multiply and 7 cycle for divide ,1 cycle for all other arithmatic operations ) and Write Back WB(1 cycle) . Assume that in a program A there ... divides,85% of othe types of instructions that take 1 cycle in execute stage . How many cycle does it take to execute program A?

asked Aug 28 in CO & Architecture by gourav94240 (23 points) | 95 views

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12

Patterson-Henessey, Pipelining
Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been written into the register file and so, there should be three stalls? From what I could understand in this question, the value of the registers is available after the M stage, before it is written.

asked Aug 17 in CO & Architecture by goxul Active (2.6k points) | 25 views

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13

Carl Hamacher Pipelining
6.9) Assume that 20 percent of the dynamic count of the instructions executed for a program are branch instructions. Assume further that 75 percent of branches are actually taken. The program is executed in two different processors that have the same ... ? (b) If the dynamic prediction accuracy is actually 90 percent, what is the speedup relative to using static prediction?

asked Jul 31 in CO & Architecture by Manish Chetwani (301 points) | 52 views

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14

packet switching
Consider the store and forward packet switched network where host A and B are connected via 2 routers R1 and R2 . Assume Transmission time to be 1ms and Propagation time of link to be 5ms. If a message is divided into 6 packets of equal length then total time to transfer message is _________ ?

asked Jul 26 in Computer Networks by Lone Wolf Active (1.1k points) | 108 views

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15

Pipeline Execution time
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 are performing multiplications, where Excution state for addition take 1 clock cycle, multiplication take 3 clock cycles ... control hazard. The number of clock cycles required for execution of sequence of instructions are ________. Ans. 454

asked Jul 22 in CO & Architecture by Na462 Loyal (6.4k points) | 65 views

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16

Pipelining
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which takes 1 clock period. In a pipelined execution of a 5-step task, a new instruction is read and ... the speedup ratio of pipe line processing system over an equivalent non pipeline processing system is ________. Ans. 4.8 Please Explain Briefly

asked Jul 21 in CO & Architecture by Na462 Loyal (6.4k points) | 72 views

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17

Pipeline Stages
The CPU supports the following instructions LOAD R1 , R2 (100) ; R2 ← [R2 + 100] ADD R1 , R2; R1 ← R1 + R2 SUB R2,R1 ; R2 ← R2 - R1 STORE R1 (100), R2 ; [R1+100] ←R2 4 stage pipeline is used to execute the above ... require 3 clocks for memory related operation and 1 clock is for other instructions. The minimum number of clocks needed with operand forwarding is ________. Ans. 11.

asked Jul 21 in CO & Architecture by Na462 Loyal (6.4k points) | 36 views

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18

Instruction Pipelining
A system employs 10 stage instruction pipeline in which 5% instruction results in data dependency, 10% instruction results in control dependency, 2% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. ... respectively. The average instruction time is ________. [in cycles] Ans. 1.92 Please Explain Briefly the Solution

asked Jul 21 in CO & Architecture by Na462 Loyal (6.4k points) | 55 views

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19

Patterson book

asked Jul 13 in CO & Architecture by soumayan bandhu Junior (743 points) | 30 views

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20

Pipeline
A computer with a 5 stage pipeline deals with conditional branches by stalling for the next 3 cycle after hitting one. how much does stalling hurt the performance is 20% of all instructions are conditional branches.

asked Jul 7 in CO & Architecture by Jaggi (81 points) | 60 views

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21

Pipeline
Suppose that a computer prefetches upto $20$ instructions in advance. on the average four of these are conditional branches, each with a probability of $90 \%$ of being predict correctly. what is the probability that the prefetching is on the right track?

asked Jul 7 in CO & Architecture by Jaggi (81 points) | 47 views

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22

#Pipelining
Consider a 5 stage pipeline that consists of IF, ID, EX, MEM and WB stages.The time taken by these stages are 20ns, 50ns, 60ns, 50ns and 20ns respectively. The pipeline registers are required after every pipeline stage and these pipeline registers ... 10ns, 20ns, 10ns, 20ns and 10ns delay. What is the speedup of the pipeline compared to the corresponding non-pipelined implementation?

asked Jul 3 in CO & Architecture by Naveen Kumar 3 Active (1.6k points) | 80 views

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3 answers

23

Pipeline Stall
Consider an instruction pipeline with five stages without any branch prediction:Fetch Instruction (FI),Decode Instruction (DI),Fetch Operand (FO),Execute Instructions (EI) and Write Operand (WO).The stage delays for each stage and delay for FI,DI,FO,EI and WO are ... I9.If the branch is taken during the execution of this program ,the time (in ns) needed to complete the program is?

asked Jul 3 in CO & Architecture by Vishnathan (189 points) | 63 views

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24

Computer Organization - Pipelining
What are stage delays in pipelining? Are they nothing but execution time required for each stage? and 'After pipelining we have to adjust the stage delays such that no stage will be waiting for another to ensure smooth pipelining (continuous flow) ' What does this statement means? Please give a brief explanation.

asked Jun 9 in CO & Architecture by Swapnil Naik Active (1.3k points) | 68 views

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25

Made Easy Test Series
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has ... 5+ (75+5-1)*3 Am i doing wrong? Solution with explanation of formulae being used will be welcomed.

asked Jun 9 in CO & Architecture by Subham Nagar Junior (669 points) | 134 views

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26

Computer organization and architecture 10th edition #Problems 14.11

asked Jun 4 in CO & Architecture by Aaron (7 points) | 54 views

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27

Pipeline
Consider a 4 stage pipeline that consists of IF,ID,EX and WB stages.The time taken by these stages are 50ns,60ns,110ns and 80ns respectively.The pipeline registers are required after every pipeline stage and each of these pipeline registers consumes 10ns delay.What is the speedup of the pipeline under ideal conditions compare to the corresponding non-pipelined implementation?

asked May 31 in CO & Architecture by Sourav_35 (201 points) | 93 views

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28

Doubt regarding the concept of pipelining

asked May 31 in Computer Networks by ejaz (217 points) | 50 views

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29

Branch Stall
What does the Following line states:- Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed. Say in below Question :- An instruction pipeline has Five Stages where each stage takes 2ns ... fetching the branch target the instruction which was incorrectly fetched will be in stage 4. Hence total 4 Stalls isn't it?

asked Apr 28 in CO & Architecture by Na462 Loyal (6.4k points) | 62 views

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30

Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help

asked Apr 19 in CO & Architecture by Na462 Loyal (6.4k points) | 122 views

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