Recent questions tagged pipelining

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1

GATEBOOK-2019 Mock Test1-46
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?

asked 10 hours ago in CO & Architecture by GATEBOOK Boss (13.5k points) | 3 views

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Instruction Pipeline
Consider an instruction pipeline with five stages , it allows overlapping of all instructions except branch type. Let there are 20% branch instructions and pipeline is operated with 800 megahertz. 1) what is the speedup? 2) what is average instruction time. 3) what is the time taken for 10 million instructions. 4) what is the throughput.

asked 16 hours ago in CO & Architecture by Nandkishor3939 Junior (791 points) | 17 views

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3

Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.

asked 17 hours ago in CO & Architecture by Nandkishor3939 Junior (791 points) | 13 views

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4

branch
a hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its task. if f is the probability of an instruction being a branch instruction then the value of f such that speed up is at least 3 is ____(upto 2 decimal places)

asked 2 days ago in CO & Architecture by Rahul_Rathod_ Junior (549 points) | 14 views

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PIPELINING
#PLEASEEXPLAINIAMNOTGETTING. Consider the following sequence of instructions executed on the five-stage pipelined processor: LW $1, 30($6) ADD $2, $4, $2 ADD $1, $3, $5 SW $2, 20($4) ADD $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

asked 3 days ago in CO & Architecture by Himanshu Kashyap (449 points) | 12 views

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made easy basic fLT 4
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)

asked 3 days ago in CO & Architecture by Satbir Active (3.1k points) | 12 views

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Madeeasy- Types of Dependencies
Please clarify along with the names.

asked Jan 9 in CO & Architecture by Markzuck (413 points) | 28 views

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How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)

asked Jan 9 in CO & Architecture by Raj Singh 1 (207 points) | 9 views

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9

Data forwarding in pipelining
Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR

asked Jan 2 in CO & Architecture by Abhilash Mishra (105 points) | 67 views

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10

Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.

asked Jan 1 in CO & Architecture by Alina (27 points) | 82 views

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Pipelining
Why pipelining cannot operate at its maximum theoretical speed? Maximum theoretical is when we say that it takes same time to process an instruction in pipeline and non pipeline circuit. So why pipelining cannot operate at its maximum theoretical speed?

asked Dec 31, 2018 in CO & Architecture by Alina (27 points) | 21 views

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12

Avoiding pipeline Hazards
Please Confirm.

asked Dec 27, 2018 in CO & Architecture by smsubham Loyal (8.9k points) | 69 views

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13

Self doubt
If the time taken by a task to get completed is same in the pipeline and non pipeline circuits, then how the time taken to complete the task in non pipeline = k* time taken to complete the task in pipeline where k is no. of segments in the pipeline?

asked Dec 27, 2018 in CO & Architecture by Nivedita Singh (35 points) | 23 views

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14

ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages ... of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825

asked Dec 25, 2018 in CO & Architecture by newdreamz a1-z0 Active (1.2k points) | 75 views

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15

Madeeasy-CO PIPELINING=OPERAND FORWARDING 2019
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)

asked Dec 25, 2018 in CO & Architecture by Markzuck (413 points) | 92 views

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16

stage delays doubt in pipelining
if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last stage. each register delay is 1ns. How the time taken by a NON-PIPELINED implementation is calculated for n no. of instructions? and what is the speed up here?

asked Dec 22, 2018 in CO & Architecture by Ashwani Yadav Junior (943 points) | 58 views

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17

Calculate speed up ratio of pipeline
Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.

asked Dec 21, 2018 in CO & Architecture by Alina (27 points) | 70 views

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18

gatebook test
Suppose the functions F and G can be computed in 8 and 3 nanoseconds by functional units UF and UG, respectively. Given three instances of UF and three instances of UG, it is required to implement the computation F(G(Xi)) for 1 ≤ i ≤ 13. A control Unit selects next task/s ... this computation is ( in nanoseconds): (A) 28 (B) 33 (C) 43 (D) 49 my answer is 43 but gatebook answer is 49.

asked Dec 18, 2018 in CO & Architecture by sushmita Boss (16.6k points) | 42 views

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19

Pipeline
A pipelined Processor contains 5 instructions stages of execution times 120ns, 160ns, 105 ns, 135ns and 155ns with a register delay 10ns on each stage. What is the percentage of performance increased with 1000 instructions instead of 10 instructions

asked Dec 18, 2018 in CO & Architecture by aditi19 Active (2.2k points) | 69 views

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20

Madeeasy [Pipelining]
Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respectively. What is average CPI of NON-PIPELINE CPU when speedup achieved by pipelined processor is 4?

asked Dec 18, 2018 in Computer Networks by jatin khachane 1 Loyal (5.6k points) | 203 views

+1 vote

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21

https://gateoverflow.in/753/gate2001-12?show=279851#c279851
doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851 In instruction I3 how is it getting the value of r2 which is computed in I1 instruction?? Can memory access stage read the value of updated register values of write back stage?? please resolve my doubt.

asked Dec 18, 2018 in CO & Architecture by sushmita Boss (16.6k points) | 45 views

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22

general doubt on pipelining
we do forwarding from WB stage to EX or from WB to MEM stage??

asked Dec 18, 2018 in CO & Architecture by sushmita Boss (16.6k points) | 42 views

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23

COA-1 ME Test Series
A system employs $10$ stage instruction pipeline in which $5$% instruction results in data dependency, $10$% instruction results in control dependency, $2$% instructions results in structural dependency. $10$% instructions are exposed to data and control ... and data dependency are $3$ clocks and $2$ clocks respectively. The average instruction time is _______ [in cycles]

asked Dec 16, 2018 in CO & Architecture by zeeshanmohnavi (373 points) | 239 views

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24

Branch Target Address
In a normal 5-stage pipeline, when is the branch target address available? There are some sources which say that the address is available after the MEM stage, but go on to say that it can be found out after the ID stage if we put in an extra ... in which they assumed that the address is available after the 4th stage. Is that the approach to be followed for all the questions?

asked Dec 11, 2018 in CO & Architecture by goxul Loyal (6k points) | 24 views

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25

pipelining
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 25% of the time for 1 cycle and 10% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI ?(ans=2.05)

asked Dec 7, 2018 in CO & Architecture by Satbir Active (3.1k points) | 86 views

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26

Pielining-Doubt
Consider below sequence of instructions $1.lw\,s2,0(s1)$ $2.lw\,s1,40(s6)$ $3.sub\,s6,s1,s2$ $4.add\,s6,s2,s2$ $5.or\,s3,s6,0$ $6.sw\,s6,50(s1)$ What is the number of clock cycles taken by above set of instructions when ... cycles (b)11 cycles Are my answers correct? Source:https://cseweb.ucsd.edu/classes/wi12/cse141-a/solutions/assignment5-soln.pdf Question 3, part 3 and 4.

asked Dec 7, 2018 in CO & Architecture by Ayush Upadhyaya Boss (22.9k points) | 103 views

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