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Recent questions tagged pipelining

5 votes
2 answers
1
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________
asked Feb 18 in CO and Architecture Arjun 714 views
0 votes
2 answers
2
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.
asked Feb 18 in CO and Architecture Arjun 329 views
0 votes
1 answer
3
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
asked Nov 20, 2020 in CO and Architecture jothee 226 views
0 votes
1 answer
4
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
asked Nov 20, 2020 in CO and Architecture jothee 168 views
0 votes
2 answers
5
2 votes
3 answers
6
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$
asked Mar 31, 2020 in CO and Architecture Lakshman Patel RJIT 603 views
0 votes
3 answers
7
Comparing the time $T1$ taken for a single instruction on a pipelined CPU, with time $T2$ taken on a non-pipelined but identical CPU, we can say that ______ ? $T1=T2$ $T1>T2$ $T1<T2$ $T1$ is $T2$ plus time taken for one instruction fetch cycle
asked Mar 30, 2020 in CO and Architecture Lakshman Patel RJIT 349 views
1 vote
5 answers
8
Consider a non-pipelined machine with $6$ stages; the lengths of each stage are $\text{20ns, 10ns, 30ns,25ns, 40 ns}$ and $\text{15ns}$ respectively. Suppose for implementing the pipelining the machine adds $\text{5 ns}$ of overhead to each stage for clock skew and set up. What is the speed up factor of the pipelining system (ignoring any hazard impact)? $7$ $14$ $3.11$ $6.22$
asked Mar 30, 2020 in CO and Architecture Lakshman Patel RJIT 1.5k views
0 votes
3 answers
9
We have $10$-stage pipeline, where the branch target conditions are resolved at stage $5$. How many stalls are there for an incorrectly predicted branch? $5$ $6$ $7$ $4$
asked Mar 30, 2020 in CO and Architecture Lakshman Patel RJIT 721 views
5 votes
1 answer
10
A non-pipelined CPU has $12$ general purpose registers $(R0,R1,R2, \dots ,R12)$. Following operations are supported $\begin{array}{ll} \text{ADD Ra, Rb, Rr} & \text{Add Ra to Rb and store the result in Rr} \end{array}$ ... $X,Y,Z$ are initially available in registers $R0,R1$ and $R2$ and contents of these registers must not be modified. $5$ $6$ $7$ $8$
asked Jan 13, 2020 in CO and Architecture Satbir 972 views
4 votes
4 answers
11
Consider a $5$- segment pipeline with a clock cycle time $20$ ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$
asked Jan 13, 2020 in CO and Architecture Satbir 2k views
0 votes
0 answers
12
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and the PC advanced. Each instruction occupies exactly ... stage and the first instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.
asked Oct 28, 2019 in CO and Architecture Lakshman Patel RJIT 323 views
1 vote
1 answer
14
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?
asked May 23, 2019 in CO and Architecture Hirak 238 views
1 vote
2 answers
15
0 votes
0 answers
16
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB
asked Mar 18, 2019 in CO and Architecture Doraemon 152 views
1 vote
1 answer
17
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE
asked Mar 8, 2019 in CO and Architecture s_dr_13 296 views
1 vote
2 answers
18
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .
asked Feb 18, 2019 in CO and Architecture DIYA BASU 237 views
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