Recent questions tagged pipelining

Recent questions tagged pipelining

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Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.

Swarnava Bose asked in CO and Architecture 3 days ago

by Swarnava Bose

26 views

0 votes

1 answer

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Pipeline Architecture
if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the pipeline? how about if the processor is divided into 50 pipeline stages?

shima abdullah asked in CO and Architecture Jun 27

by shima abdullah

56 views

4 votes

2 answers

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GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.

Arjun asked in CO and Architecture Feb 15

by Arjun

1.5k views

3 votes

0 answers

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#pipeline #self doubt
Consider a 5—stage pipeline processor used to execute 200 number of instructions and among those 100 instructions cause 3 stall cycles each. What is the total cycles required for these operation if CPI is not equal to one.

jayadev asked in CO and Architecture Feb 3

175 views

2 votes

2 answers

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Made Easy Test Series
Consider a pipeline consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline y' contain the same number of stages but EX stage is divided into 2 ... the program contain 20% of the instructions which are memory based instructions, what is the ratio of speed-up of x to speed-up of y?

LRU asked in CO and Architecture Jan 20

by LRU

209 views

2 votes

2 answers

6

Made Easy Test Series
Consider 5 stage pipelined processor has instruction fetch (IF), Instruction decode (ID), Operand fetch (OF), Perform operation (PO) and Write operand (WB) stages. The IF, ID, OF and WB stages takes 1 clock cycle each for any ... instructions respectively. How many clock cycles needed to execute the above sequence of instruction, where operand forwarding from PO to PO?

LRU asked in CO and Architecture Jan 20

by LRU

191 views

0 votes

1 answer

7

Applied Test Series
Consider the following sequence of instructions: LOAD R4, 0(R8) AND R1, R5, R2 OR R1, R1, R3 OR R2, R2, R7 ADD R3, R2, R1 STORE R3, 0(R8) Number of cycles required to complete the given sequence of instructions in a 5 stage (IF, ID, EX, Mem, WB) RISC processor with operand forwarding_____

LRU asked in CO and Architecture Jan 8

by LRU

180 views

0 votes

1 answer

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Applied Test Series
Consider the following sequence of instructions Add #20,R0,R1 Mul #3,R2,R3 And # ... fetch(other stages also) requires only one clock cycle. Number of cycles required to complete the given sequence of instructions are_____

LRU asked in CO and Architecture Jan 8

by LRU

143 views

0 votes

2 answers

9

Self doubt Pipelining
Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i<=1) {I1,I2,I3,I4} where i=0. Time (ns) taken by the instruction I1 to I4 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 I1 1 1 2 1 1 I2 1 2 1 1 1 I3 1 2 2 1 1 I4 2 1 2 1 1 Output of I4 will be available at $_____$.

Divyanshu Shukla asked in CO and Architecture Jan 6

by Divyanshu Shukla

173 views

0 votes

0 answers

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speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption

farmanahmed888 asked in CO and Architecture Jan 6

by farmanahmed888

138 views

0 votes

1 answer

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COA Applied Course
Assume that we are using the classic MIPS five-stage(IF, ID, EX, MEM and WB) integer pipeling.

Sagar475 asked in CO and Architecture Dec 26, 2021

110 views

1 vote

1 answer

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Test Series: ACE
How to approach this one?

ramakrushna asked in CO and Architecture Dec 23, 2021

150 views

0 votes

1 answer

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Computer System Architecture By M Morris Mano
The floating-point pipeline are implemented with combinational circuits.Suppose that the time delays of the four segments are t1=60ns, t2=70ns, t3=100ns, t4=80ns, and the interface registers have a delay of tr=10ns. Solution: Pipeline floating-point ... t3+t4+tr=320ns  Speedup: 320/110=2.9 My Doubt: why register delay is added in non pipeline system?

Divyanshu Shukla asked in CO and Architecture Dec 16, 2021

by Divyanshu Shukla

226 views

0 votes

1 answer

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ISRO | ISRO CS 2020 | Question 6
Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (If an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline.). (A) 5 (B) 4.03 (C) 4.81 (D) 4.17

ProtonicRED asked in CO and Architecture Dec 14, 2021

140 views

1 vote

1 answer

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GATE appliedroots test series
I have 3 doubts in the following solution: Doubt 1: In red colour While I1 is in the Memory-access stage, how can I4 fetch the instruction from the memory? Isn't this a structural dependency problem? Doubt 2: In blue colour We ... I5 operate with register only so the memory-access stage shouldn't happen for these instructions, correct? Solution as per my understanding:

Ashutosh_Mishra asked in CO and Architecture Dec 12, 2021

by Ashutosh_Mishra

186 views

0 votes

0 answers

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NPTEL Assignment Question
Consider the following code : Load R1,M Load R2,N CMP R1,R2 JGE END Store [300],R2 END: Store [300],R1 Assume that M=30 and N=25. The above sequence of instructions is to be executed on a pipelined processor with IF , ... instructions. The branch outcome is known after EX stage. Determine the number of clock cycles required for completion of execution of all instructions.

rsansiya111 asked in CO and Architecture Dec 8, 2021

93 views

0 votes

2 answers

17

Gate Applied Course Test Series
A 5-stage(IF,ID, EX, MEM and WB) MIPS pipeline has a register file without forwarding mechanism.How Many NOPs (or bubbles) will you need to add to make this code work correctly Lw $1, 40($6) Add $6,$2, $2 SW $6, 50($1) //$6 → M[$1+50] A)1 B) 2 C)0 D) 3

Dheeraj Varma asked in CO and Architecture Nov 25, 2021

by Dheeraj Varma

228 views

1 vote

2 answers

18

Doubt regarding pipeline
Hi, I have a question like how Load/Store operation behave in pipelining, with or without operand forwarding ?

Nihal Singh asked in CO and Architecture Oct 26, 2021

406 views

0 votes

1 answer

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Applied Test Series
Suppose that we are considering an enhancement that runs 10 times faster than the original machine but is usable only 40% of the time. What is the overall speedup gained by incorporating the enhancement.

LRU asked in CO and Architecture Oct 23, 2021

by LRU

229 views

0 votes

0 answers

20

William Stallings - Computer Organization and Architecture D
A computer system contains a main memory of 32KB. It also has a 4KB cache divided into four-lines/set with 64B per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . . ... from the use of the cache. Assume an LRU policy for block replacement. Show the state of cache at the end.

lucifer069 asked in CO and Architecture Sep 16, 2021

143 views

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0 answers

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William Stallings - Computer Organization and Architecture D
Consider the following assembly code: Instruction Description LD R1, 45(R2) Read data from memory and store in R1. Memory address is calculated by adding 45 to the content of R2 ADD R7, R1, R5 Add contents of R1 ... Calculate the execution time and compare time that would have required in a non-pipelined processor to run the same program.

lucifer069 asked in CO and Architecture Sep 16, 2021

129 views

0 votes

2 answers

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UGC NET CSE | December 2019 | Part 2 | Question: 9
A non-pipelined system takes $\text{30ns}$ to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of $\text{10ns}$. Determine the speed up of the pipeline for $100$ tasks. $3$ $4$ $3.91$ $2.91$

soujanyareddy13 asked in Others May 12, 2021

by soujanyareddy13

500 views

10 votes

3 answers

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GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

6.0k views

5 votes

2 answers

24

GATE CSE 2021 Set 1 | Question: 53
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

2.2k views

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