Recent questions tagged pipelining

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1

Computer Organization - Pipelining
What are stage delays in pipelining? Are they nothing but execution time required for each stage? and 'After pipelining we have to adjust the stage delays such that no stage will be waiting for another to ensure smooth pipelining (continuous flow) ' What does this statement means? Please give a brief explanation.

asked Jun 9 in CO & Architecture by Swapnil Naik (39 points) | 19 views

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2

Made Easy Test Series
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has ... 5+ (75+5-1)*3 Am i doing wrong? Solution with explanation of formulae being used will be welcomed.

asked Jun 9 in CO & Architecture by Subham Nagar Junior (533 points) | 34 views

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3

Computer organization and architecture 10th edition #Problems 14.11

asked Jun 4 in CO & Architecture by Aaron (7 points) | 34 views

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2 answers

4

Pipeline
Consider a 4 stage pipeline that consists of IF,ID,EX and WB stages.The time taken by these stages are 50ns,60ns,110ns and 80ns respectively.The pipeline registers are required after every pipeline stage and each of these pipeline registers consumes 10ns delay.What is the speedup of the pipeline under ideal conditions compare to the corresponding non-pipelined implementation?

asked May 31 in CO & Architecture by Sourav_35 (199 points) | 46 views

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1 answer

5

Doubt regarding the concept of pipelining

asked May 31 in Computer Networks by ejaz (175 points) | 32 views

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6

Branch Stall
What does the Following line states:- Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed. Say in below Question :- An instruction pipeline has Five Stages where each stage takes 2ns ... fetching the branch target the instruction which was incorrectly fetched will be in stage 4. Hence total 4 Stalls isn't it?

asked Apr 28 in CO & Architecture by Na462 Active (3.3k points) | 34 views

+1 vote

1 answer

7

Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help

asked Apr 19 in CO & Architecture by Na462 Active (3.3k points) | 91 views

+1 vote

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8

Pipeline
Say Machine with 10ns click and takes 4 cycles for AlU and other operations. When we talk about the time taken by pipelined processor it is = the highest time taken by a stage + overhead We took the highest time only because we know that there is no stalling so ... plz explain why then CPI is one in all cases when stalls aren't there. And plz explain the cpi for non pipelined processor .

asked Apr 19 in CO & Architecture by Na462 Active (3.3k points) | 55 views

+1 vote

2 answers

9

pipelining
A CPU has five-stage pipeline where each stage takes $1\hspace{0.1cm}ns$, $2\hspace{0.1cm}ns$, $1.5\hspace{0.1cm} ns$, $3\hspace{0.1cm}ns$, $2.5\hspace{0.1cm} ns$. Instruction fetch happens in the first stage of the pipeline. A ... one clock cycle. $30\%$ of the instructions are conditional branches. Find the average execution time of the program for $1200$ instructions is ________.

asked Mar 29 in CO & Architecture by Amit puri Active (2.9k points) | 230 views

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1 answer

10

Pipeline Stall
I am very Confused in determining the number of stalls in a given execution. Please determine how to find out the number of stalls in the execution of the pipeline. Like In this example calculate the number of stalls:- I successfully calculated the total clock cycle but plz indicate number of ... place ? Instruction Fetch Decode Execute Write 1 1 2 2 1 2 2 3 3 2 3 3 1 1 1 4 1 1 1 1

asked Mar 16 in CO & Architecture by Na462 Active (3.3k points) | 112 views

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11

Pipeline
@Arjun sir In the Question :- https://gateoverflow.in/1391/gate2005-68 I have drawn like :- F D E M W F D D E M W F - D E M W Total 8 Clock cycle with operand forwarding. Why cant we Overlap stuffs means:- In first case at second instruction ... cycles. Checkout the comment of Arjun Sir:- https://gateoverflow.in/3623/gate2006-it-79 Or when to use such technique as depicted by Arjun Sir.

asked Mar 13 in CO & Architecture by Na462 Active (3.3k points) | 48 views

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0 answers

12

Pipeline Stalls
I am very Confused to how to calculate Delay SLOTS in a given Pipeline. Can anybody explain the technique for finding the number of delay slots and Stalls in A pipelined processor. 2. Is delay slot and pipeline stall the same thing. Because delay slot is created using branch ... - --- I4 = F D E M W So 3 stalls right? what about Pipeline stalls?? Plz explain where i am wrong?

asked Mar 13 in CO & Architecture by Na462 Active (3.3k points) | 49 views

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1 answer

13

Pipeline
In question like say "I have $4$ stages with delay $1,2,3,4 \hspace{0.1cm}ns$ and total instructions are $100$. Calculate the total time?" In such questions by default we consider a synchronous pipeline processor right? that why we apply $(k+n-1)*tp$ ??

asked Mar 13 in CO & Architecture by Na462 Active (3.3k points) | 58 views

+11 votes

3 answers

14

GATE2018-50
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB), The IF, ID, OF and WB stages take 1 clock cycle each for ... no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____

asked Feb 14 in CO & Architecture by gatecse Boss (18k points) | 2k views

+1 vote

1 answer

15

Gate 2018
Consider instruction pipeline with five stages $\text{instruction fetch (IF), Instruction Decode (ID), Operand Fetch (OF)}$, $\text{perform operation (PO), and write back (WB)}$. There are $100$ instructions, perform operation stage (PO) takes $3$ ... $40, 25, 35, $ instruction respectively other stages takes one clock for each. Number of clocks is needed for this pipeline________.

asked Feb 6 in CO & Architecture by jatin khachane 2 (57 points) | 623 views

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0 answers

16

Gfg Mock test 1
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ... . If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .

asked Feb 1 in CO & Architecture by Utsav09 Active (1.1k points) | 70 views

+1 vote

0 answers

17

Mulitsubject CO and CN
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 KB and the threshold at the start of first transmission is 24 KB. Assume that 3 duplicate ACK are received during the 5th ... WB and ID stage i.e. in one half of cycle doing WB and in another half doing ID. Given answer is 14.

asked Jan 26 in Programming by Shubhanshu Boss (15k points) | 84 views

+2 votes

1 answer

18

Pipeline hazards
R1 <- R1+R2 R2 <- R3*R4 R3 <- R4-R1 R2 <- R3+R4 Can someone point out hazards. Thanks :)

asked Jan 25 in CO & Architecture by gauravkc Loyal (5.4k points) | 85 views

+2 votes

1 answer

19

COA: Number of RAW hazards
Consider the following Instruction sequence I1: ADD R1,R2,R1 I2: LW R2,0(R1) I3: LW R1,4(R1) I4: OR R3,R1,R2 And assume following five stage pipeline with following stages: IF,ID,EXE,MEM,WB The no of RAW hazards in the above Instruction sequence is? (A) 3 (B) 2 (C) 4 (D) 1 Note:- I think there are 2 RAW hazards, b/w I1 & I2 and I3&I4.

asked Jan 20 in CO & Architecture by Vijay Thakur Boss (17.1k points) | 115 views

+2 votes

0 answers

20

number of instructions must be inserted to achieve CPI = 1 by using operand forwarding

asked Jan 19 in CO & Architecture by Tuhin Dutta Loyal (7.9k points) | 95 views

+2 votes

0 answers

21

Self Doubt
What effect does Loop Unrolling have on the ans? What is the ans if we don't use it?

asked Jan 16 in CO & Architecture by vishal chugh Active (1.7k points) | 23 views

+3 votes

1 answer

22

CO-Pipelining
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ... I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .

asked Jan 16 in CO & Architecture by AnilGoudar Active (4.4k points) | 163 views

+1 vote

1 answer

23

Co & Arch

asked Jan 15 in CO & Architecture by gauravkc Loyal (5.4k points) | 78 views

+3 votes

0 answers

24

pipelining
is it 1.92 or 1.94 i want conformation...

asked Jan 15 in CO & Architecture by pranab ray Junior (895 points) | 55 views

+2 votes

0 answers

25

#Data Hazards #Operand Forwarding #CO
Is there any difference in calculating data hazards and dependencies? Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS TRUE. Doubt 2:Calculation of RAW,WAR,WAW hazards include all ... adjacent.IS THIS TRUE There are many sources which are confusing Please Explain how to calculate dependencies and hazards.

asked Jan 13 in CO & Architecture by Deepak Mokili (307 points) | 62 views

+3 votes

0 answers

26

Speedup In pipelining
Actually, In this problem what will, we consider getting the answer(upper bound or lower bound) and why?

asked Jan 13 in CO & Architecture by thepeeyoosh Active (2k points) | 73 views

+1 vote

0 answers

27

pipielining
In questions where we are asked to find number of cycles taken for a set of instructions, if an IF overlaps with MEM (which generally is a structural hazard) we still let it overlap in the solution. So does IF and MEM execute in split phase? If so I have read ... (a comment by someone) that it takes one whole cycle for MEM to function and cannot be in a split phase? Please help me out.

asked Jan 13 in CO & Architecture by Warlock lord Active (3.4k points) | 27 views

+2 votes

2 answers

28

pipelining
We have two designs P 1 and P 2 for a synchronous pipeline processor. P1 has 8 pipeline stages with execution time of 3 nsec, 2 nsec, 4 nsec, 7 nsec, 2 nsec, 5 nsec, 4 nsec and 2 nsec while design P2 has 5 stages each with 6 nsec execution time. How much time can be saved using design P2 over design P1 for executing 400 instructions?

asked Jan 2 in CO & Architecture by Parshu gate Active (4.9k points) | 64 views

+2 votes

1 answer

29

pipelining
Assume branch instructions occur 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% of the time with ... instructions are loads and 30% of these introduce load delay hazards. What is the New CPI due to load delay slots and branch hazards?

asked Jan 1 in CO & Architecture by Parshu gate Active (4.9k points) | 68 views

+1 vote

0 answers

30

Test Series

asked Jan 1 in CO & Architecture by Kalpataru Bose (337 points) | 56 views

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