Recent questions tagged pipelining

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1

Pipeline speedup
Consider a nonpipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is

asked 21 hours ago in CO & Architecture by Kartavya Kothari (123 points) | 33 views

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2

Control Dependencies
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asked 3 days ago in CO & Architecture by Lakshmi kittur (61 points) | 82 views

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3

Data Hazard

asked 3 days ago in CO & Architecture by Na462 Loyal (6.9k points) | 27 views

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4

Control dependencies
Consider a pipelined processor having 5 stages. The stage delays are 2, 3, 2.5, 3.2, 2.5ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding branch target address. Processor starts fetching new instruction when the conditional branch outcome is known. 20% of instructions are conditional branch, then calculate the execution time for 1000 instructions?

asked 4 days ago in CO & Architecture by Lakshmi kittur (61 points) | 79 views

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5

PIPELINE Doubt
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and branches are taken 75%of time. what would be the expected cpi?

asked Nov 10 in CO & Architecture by rishabhdevsingh1 (83 points) | 45 views

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6

pipeline
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and branches are taken 75%of time. what would be the expected cpi?

asked Nov 10 in CO & Architecture by rishabhdevsingh1 (83 points) | 22 views

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2 answers

7

Pipelining

asked Nov 7 in CO & Architecture by Na462 Loyal (6.9k points) | 69 views

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8

Pipeline : Number of RAW dependencies
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding. I1: ADD R0,R1,R2 (R0=R1+R2) I2: SUB R3,R0,R2 I3:MUL R4,R3,R0 I4:DIV R5,R4,R0 How many RAW dependencies?

asked Oct 23 in CO & Architecture by Mk Utkarsh Boss (23.6k points) | 88 views

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9

DOUBT: isn't this is a pipelining question

asked Oct 18 in CO & Architecture by Ashwani Yadav (301 points) | 31 views

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10

Operand Forwarding
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage takes one cycle. How many instructions must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6

asked Oct 13 in CO & Architecture by Na462 Loyal (6.9k points) | 70 views

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11

Is superscalar operations in pipelining part of gate syllabus

asked Oct 4 in CO & Architecture by bts1jimin (101 points) | 23 views

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12

Branch prediction in pipelining part of syllabhs?

asked Oct 3 in CO & Architecture by bts1jimin (101 points) | 32 views

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13

Pipeline performance reduced if different stages have different execution delays

asked Oct 2 in CO & Architecture by Harsh Kumar Junior (803 points) | 27 views

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14

Minimum clock cycle

asked Sep 24 in CO & Architecture by Na462 Loyal (6.9k points) | 80 views

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15

#CO pipeline doubt
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute the following loop? For (i=1 to 2){I1; I2; ... stage, the current instruction(I4) cannot execute a given stage P.S.- Refer here- https://gateoverflow.in/244642/%23co-gate-2009-self-doubt

asked Sep 21 in CO & Architecture by iarnav Loyal (9k points) | 53 views

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16

#CO Gate 2009 Self Doubt.
Original question- https://gateoverflow.in/1314/gate2009-28 In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stage? In this question if we take the above approach, we will get different ... , Refer this GATE 2004-IT question- https://gateoverflow.in/3690/gate2004-it-47 in this we are doing as the above approach.

asked Sep 19 in CO & Architecture by iarnav Loyal (9k points) | 32 views

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17

Self Doubt : Pipe lining
Given 100 instructions executed on a 5 stage pipeline . probability (p) that an instruction is branch is p. Branch penalty 4.Assuming that each stage of pipeline takes 1 cycle.Calculate total execution time. My query is since first instruction will take 5 clk so how to calculate ? is 5+ 99[(1-p)*1 + p*4] the correct approach ?

asked Sep 8 in CO & Architecture by Shiv Gaur Active (1.4k points) | 35 views

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18

Operand Forwarding Doubt
I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??

asked Sep 3 in CO & Architecture by Na462 Loyal (6.9k points) | 38 views

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19

Pipeline Doubt
Its a snapshot from hamacher. According to me there should be stall of 2 cycles why 3 ?? Because after Write stage the data will be available in register file so why extra stall in 6th clock cycle ?

asked Sep 3 in CO & Architecture by Na462 Loyal (6.9k points) | 53 views

+1 vote

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20

COA -INSTRUCTION PIPELINE
Consider a 4 stage pipeline:fetch-IF(2cycle), decode& read -ID(1 cycle) execute-Ex(4 cycle for multiply and 7 cycle for divide ,1 cycle for all other arithmatic operations ) and Write Back WB(1 cycle) . Assume that in a program A there ... divides,85% of othe types of instructions that take 1 cycle in execute stage . How many cycle does it take to execute program A?

asked Aug 28 in CO & Architecture by gourav94240 (35 points) | 111 views

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21

Patterson-Henessey, Pipelining
Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been written into the register file and so, there should be three stalls? From what I could understand in this question, the value of the registers is available after the M stage, before it is written.

asked Aug 17 in CO & Architecture by goxul Active (4.2k points) | 31 views

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22

Carl Hamacher Pipelining
6.9) Assume that 20 percent of the dynamic count of the instructions executed for a program are branch instructions. Assume further that 75 percent of branches are actually taken. The program is executed in two different processors that have the same ... ? (b) If the dynamic prediction accuracy is actually 90 percent, what is the speedup relative to using static prediction?

asked Jul 31 in CO & Architecture by Manish Chetwani (305 points) | 66 views

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23

packet switching
Consider the store and forward packet switched network where host A and B are connected via 2 routers R1 and R2 . Assume Transmission time to be 1ms and Propagation time of link to be 5ms. If a message is divided into 6 packets of equal length then total time to transfer message is _________ ?

asked Jul 26 in Computer Networks by Lone Wolf Active (1.1k points) | 116 views

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1 answer

24

Pipeline Execution time
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 are performing multiplications, where Excution state for addition take 1 clock cycle, multiplication take 3 clock cycles ... control hazard. The number of clock cycles required for execution of sequence of instructions are ________. Ans. 454

asked Jul 22 in CO & Architecture by Na462 Loyal (6.9k points) | 116 views

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1 answer

25

Pipelining
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which takes 1 clock period. In a pipelined execution of a 5-step task, a new instruction is read and ... the speedup ratio of pipe line processing system over an equivalent non pipeline processing system is ________. Ans. 4.8 Please Explain Briefly

asked Jul 21 in CO & Architecture by Na462 Loyal (6.9k points) | 94 views

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26

Pipeline Stages
The CPU supports the following instructions LOAD R1 , R2 (100) ; R2 ← [R2 + 100] ADD R1 , R2; R1 ← R1 + R2 SUB R2,R1 ; R2 ← R2 - R1 STORE R1 (100), R2 ; [R1+100] ←R2 4 stage pipeline is used to execute the above ... require 3 clocks for memory related operation and 1 clock is for other instructions. The minimum number of clocks needed with operand forwarding is ________. Ans. 11.

asked Jul 21 in CO & Architecture by Na462 Loyal (6.9k points) | 46 views

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27

Instruction Pipelining
A system employs 10 stage instruction pipeline in which 5% instruction results in data dependency, 10% instruction results in control dependency, 2% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. ... respectively. The average instruction time is ________. [in cycles] Ans. 1.92 Please Explain Briefly the Solution

asked Jul 21 in CO & Architecture by Na462 Loyal (6.9k points) | 86 views

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28

Patterson book

asked Jul 13 in CO & Architecture by soumayan bandhu Junior (769 points) | 35 views

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29

Pipeline
A computer with a 5 stage pipeline deals with conditional branches by stalling for the next 3 cycle after hitting one. how much does stalling hurt the performance is 20% of all instructions are conditional branches.

asked Jul 7 in CO & Architecture by Jaggi (81 points) | 68 views

+1 vote

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30

Pipeline
Suppose that a computer prefetches upto $20$ instructions in advance. on the average four of these are conditional branches, each with a probability of $90 \%$ of being predict correctly. what is the probability that the prefetching is on the right track?

asked Jul 7 in CO & Architecture by Jaggi (81 points) | 54 views

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