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Pipelining Explained

Recent questions tagged pipelining

25 25 votes
4 answers 4 answers
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GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third...
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1 1 vote
1 1 answer
2.1k
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Operand forwarding Made Easy Question
Consider 4-stage (IF, ID, EX, WB) pipeline used to execute the following code. All instructions are spending are spending one cycle on all the stages but ALU instructions...
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14 14 votes
4 4 answers
2.7k
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GO Classes CS Test Series | Mock GATE | Test 4 | Question: 20
Consider the following instruction sequence in a single-issue in-order $5$-stage pipeline $\text{(IF, ID, EX, MEM, and WB)}.$$$\begin{array}{ccccc}\text { Opcode } & \tex...
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1 1 vote
1 answers 1 answer
777
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PERSONAL DOUBT [PIPELINING]
So I know pipelining has 5 stages: IF, ID, EX, MA, WB.Now the question is if I have a program of few instruction which has both ALU operation and LOAD/store operation in ...
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0 0 votes
0 0 answers
536
536 views
Calcutta University Question Paper
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MA...
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2 2 votes
3 3 answers
1.7k
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CO and Arcitecture | RISC | Instruction pipelining
MSQWhich among the following statements is/are TRUE for a pipelined RISC computer.PC is usually incremented during Instruction Cycle (IF,ID)PC may be incremented during ...
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1 1 vote
1 1 answer
981
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Computer Organization and architecture
Consider a hypothetical processor which supports expand opcode technique. A 32bit instruction is place in 256MW memory. If there exist 10, one address instructionthen how...
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0 0 votes
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617
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University Assignment
𝑙𝑜𝑜𝑝:1. 𝐴𝐷𝐷𝐼 𝑅2, 𝑅2, #12. 𝐿𝐷 𝑅4, 0(𝑅3)3. 𝐿𝐷 𝑅5, 4(𝑅3)4. 𝐴𝐷𝐷 𝑅6, 𝑅4, 𝑅55. 𝑀𝑈𝐿 𝑅4, 𝑅6, 𝑅76. 𝑆𝑈𝐵𝐼 𝑅3, 𝑅3, #87. 𝐵𝑁𝐸𝑍 𝑅2, 𝑙𝑜𝑜𝑝8. 𝐴𝐷𝐷 𝑅11, 𝑅12, 𝑅13Question: Assume a 5-stage pi...
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1 1 vote
1 1 answer
751
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UGC NET CSE | October 2022 | Part 1 | Question: 8
A $4$-stage pipeline has the stage delay as $150,120,160$ and $140$ ns respectively. Registers that are used between the stages have delay of $5 \mathrm{~ns}$. Assuming c...
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0 0 votes
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pipelining with branch instructions
ADD R1,R2,R3SUB R2,R1,R7BNEQZ R5,L1MUL R8,R9,R3DIV R6,R8,R7L1:-LOAD R4, 2(R6)SUB R10,R4,R11 for the above sequence of instructions draw time and space diagram to find out...
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2 2 votes
1 answers 1 answer
886
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Gate@Zeal 2022
Answer 1.03
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1 1 vote
2 answers 2 answers
815
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Gate@Zeal 2022 Test Series
Answer 1.18
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0 0 votes
0 0 answers
517
517 views
Gate@Zeal 2022
Answer 1.125
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0 0 votes
0 0 answers
606
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Gate@Zeal 2022 Test Series
Answer (A)
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1 1 vote
1 1 answer
763
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Madeeasy Test Series 2023
Answer: 1.098
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0 0 votes
0 0 answers
841
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Gate@Zeal Test Series 2022
Answer 3.12Consider a classical 5-stage pipeline processor. A program consists of 25,000 instructions are executed on this processor. Assume that:- 4500 of those instruct...
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4 4 votes
1 1 answer
1.2k
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Gate At Zeal
Consider a classical 5-stage pipeline processor. A program consists of 25,000 instructions are executed on this processor. Assume that:- 4500 of those instructions are br...
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