Recent questions tagged pipelining

here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to u...

if a instruction pipeline has 5 stages with different stage delays 2 , 3 , 4 , 5, 6 ns . The pipeline registers are required between each stage and at the end of last sta...

4 stage pipeline with respective delays of 2 ns , 8 ns , 3 ns , 1 ns .It is enhanced to improve the performance with stages , but in the enhancement process longest dela...

Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with proce...

Minimum number of stages in a pipeline processor that achieve a speed of 9.2 for 200 operations is

Consider execution of 100 instructions on a 5 stage pipeline. let P be the probability of an instruction being branch. The value of P such that speed up is atleast 4 is__...

Suppose the functions F and G can be computed in 8 and 3 nanoseconds by functional units UF and UG, respectively. Given three instances of UF and three instances of UG, i...

Consider a 5 stage pipeline with Instruction Fetch(IF),Instruction decode(ID),Execute(EX),Write back(WB),and Memory access(MA) having latencies(in ns) 3,8,5,6 and 4 respe...

we do forwarding from WB stage to EX or from WB to MEM stage??

Consider a 5 stage pipeline that allows overlapping of all instructions except branch instructions. The target of branch instructions is not available until the branch in...

Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay. The p...

Consider below sequence of instructions$1.lw\,s2,0(s1)$$2.lw\,s1,40(s6)$$3.sub\,s6,s1,s2$$4.add\,s6,s2,s2$$5.or\,s3,s6,0$$6.sw\,s6,50(s1)$What is the number of clock cycl...

Is Cycles required 11 or 14 ?

Consider a non­pipelined processor design which has a cycle time of 10ns and average CPI of1.4. The maximum speedup pipelined processor can get by pipelining it into 5 st...

Consider a pipelined processor having 5 stages. The stage delays are 2, 3, 2.5, 3.2, 2.5ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding bran...