Recent questions tagged clock-frequency - GATE Overflow

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Maximum Clock Rate
Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz

asked Jan 19, 2018 in Digital Logic by Tuhin Dutta | 219 views

+1 vote

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2

maximum clock rate
What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz

asked Jan 19, 2018 in Digital Logic by Tuhin Dutta | 143 views

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2 answers

3

Output clock frequency

asked Dec 6, 2017 in Digital Logic by Parshu gate | 557 views

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0 answers

4

MadeEasy Subject Test: CO & Architecture - Clock Frequency
I got 34 as answer, but given is 35.

asked Nov 7, 2017 in CO and Architecture by rahul sharma 5 | 153 views

+4 votes

2 answers

5

gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?

asked Feb 7, 2017 in CO and Architecture by Purple | 926 views

+4 votes

1 answer

6

gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8

asked Feb 7, 2017 in CO and Architecture by Purple | 757 views

+1 vote

1 answer

7

MadeEasy Workbook: CO & Architecture - Clock Frequency

asked Feb 1, 2017 in CO and Architecture by Smriti012 | 97 views

0 votes

1 answer

8

MadeEasy Workbook: CO & Architecture - Clock Frequency

asked Feb 1, 2017 in CO and Architecture by Smriti012 | 105 views

+1 vote

1 answer

9

Virtual Gate Test Series: Digital Logic - Flip Flop Delay

asked Jan 18, 2017 in Digital Logic by Sheshang | 179 views

0 votes

1 answer

10

Ace Test Series: Digital Logic - Digital Counter

asked Dec 25, 2016 in Digital Logic by sourojit | 134 views

0 votes

2 answers

11

Frequency of output signal?
I got the ans as 1/(5*25) = 1/125. None of the, match

asked Dec 19, 2016 in Digital Logic by prasitamukherjee | 229 views

+2 votes

1 answer

12

Clock frequency required for proper operation of ripple counter
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper operation of counter is? (A) 1 MHz (B) 500 MHz (C) 1.5 MHz (D) 2 MHz

asked Oct 18, 2016 in Digital Logic by GateAspirant999 | 2.7k views

+8 votes

1 answer

13

Counters+Frequency

asked Oct 13, 2016 in Digital Logic by Rahul Jain25 | 1.7k views

+1 vote

1 answer

14

MadeEasy Test Series: CO & Architecture - Clock Frequency
Consider 1 GHz clock frequency processor, uses different operand accessing models shown below: Assume that 2 memory cycles consumed for memory reference, 3 cycles consumed for arithmetic computation and 1 cycle consumed when the operand is in ... (in million words/sec) of processor is __________ (upto 2 to decimal places).(ANSWER-344.82)

asked Jan 29, 2016 in CO and Architecture by sourav. | 657 views

+1 vote

1 answer

15

Maximum clock frequency for the circuit
In the following digital circuit shown above, the worst case delay is of 30 nsec and the AND gate has delay of 10 nsec. The maximum clock frequency of the circuit to operate is _ MHz. I calculated as follows : ... the flip-flop delay once? The solution gives the frequency as 14.2 MHz, adding the delay due to flip-flop twice. Why?

asked Jan 17, 2016 in Digital Logic by Utk | 1.1k views

+1 vote

1 answer

16

What is the o/p according to given timing diagram?
a) A = 0, 1, 0, 0, B = 1, 0, 1, 1 b) A = 1, 0, 1, 1, B = 0, 1, 0, 0 c) A = 1, 1, 0, 0, B = 1, 1, 0, 0 d) A = 0, 1, 0, 0, B = 0, 1, 0, 0 I thought it would be (c) as previous states should persist for 1st clock. But answer given is (a). Can somebody please explain??

asked Dec 30, 2015 in Digital Logic by Tushar Shinde | 325 views

+1 vote

1 answer

17

Whether to count MegaByte as 2^20 or 10^6
The first word of the memory block (each block contains 4 words of 4 bytes each) takes 5 clock cycles and remaining 3 words are transferred in consecutive cycles. Given the clock rate is 100 MHz. The data rate (in MBps) of memory for transferring one ... Please give me reference for that ! (So I can be happy :D ) From Made Easy FLT 6-Practice Test 14 Q 61

asked Dec 1, 2015 in CO and Architecture by Akash Kanase | 175 views

+4 votes

2 answers

18

Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of ... reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?

asked Oct 27, 2015 in CO and Architecture by khushtak | 3.1k views

+4 votes

1 answer

19

Drd0 2008 q-11 ch-3 i/o interface
In an n- CPU shared bus system, if z is the probability that any CPU requests the bus in a given cycle, the probability that only one CPU uses the bus is given by- A. Nz(1-z)n-1 B. Z(1-z)n-1 C. N(1-z)n D. (N-1)z(1-z)n

asked Oct 20, 2015 in CO and Architecture by khushtak | 392 views

+2 votes

1 answer

20

Q 37 me ch-5
A hierarical cache memory subsystem has a cache access time of 50ns and the main storage access time is of 500ns . with the read hit ratio of 0.9, what is the average access time of the system considering only memory read cycle in the write through scheme? a. 10 ns b. 100 ns c. 50ns d. 500ns

asked Oct 20, 2015 in CO and Architecture by khushtak | 255 views

+6 votes

2 answers

21

Made Easy CA pipeline q2
A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the throughout of the system if 20% of instructions are branch instructions ignore the ... of 4 cycles. A.55 MIPS B.45 MIPS C. 65 MIPS D. None of these. (explain the solution as well)

asked Oct 20, 2015 in CO and Architecture by khushtak | 1.6k views

+1 vote

1 answer

22

Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40

asked Oct 7, 2015 in CO and Architecture by khushtak | 1k views

+21 votes

2 answers

23

GATE2007-IT-36
The floating point unit of a processor using a design $D$ takes $2t$ cycles compared to $t$ cycles taken by the fixed point unit. There are two more design suggestions $D_1$ and $D_2$. $D_1$ uses $30\%$ more cycles for fixed point unit but $30\%$ less cycles for floating point unit as ... $D_j$) $D_1 > D > D_2$ $D_2 > D > D_1$ $D > D_2 > D_1$ $D > D_1 > D_2$

asked Oct 30, 2014 in CO and Architecture by Ishrat Jahan | 2.4k views

+13 votes

1 answer

24

GATE1992-01-iii
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because _____

asked Sep 13, 2014 in CO and Architecture by Kathleen | 903 views

+7 votes

1 answer

25

Clock-frequency
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because ?

asked Sep 3, 2014 in CO and Architecture by srinath | 795 views

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