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Recent questions tagged clock-frequency
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Maximum Clock Rate
Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
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Jan 18, 2018
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Digital Logic
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Tuhin Dutta
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maximum clock rate
What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
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Jan 18, 2018
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Digital Logic
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Tuhin Dutta
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Output clock frequency
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Dec 6, 2017
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Digital Logic
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Parshu gate
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digital-logic
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4
MadeEasy Subject Test: CO & Architecture - Clock Frequency
I got 34 as answer, but given is 35.
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Nov 6, 2017
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CO and Architecture
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rahul sharma 5
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clock-frequency
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5
gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?
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Feb 7, 2017
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CO and Architecture
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Purple
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gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8
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Feb 7, 2017
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Purple
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MadeEasy Workbook: CO & Architecture - Clock Frequency
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Feb 1, 2017
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CO and Architecture
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Smriti012
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MadeEasy Workbook: CO & Architecture - Clock Frequency
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Feb 1, 2017
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CO and Architecture
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Smriti012
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made-easy-booklet
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9
Virtual Gate Test Series: Digital Logic - Flip Flop Delay
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Jan 18, 2017
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Digital Logic
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Sheshang
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Ace Test Series: Digital Logic - Digital Counter
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Dec 24, 2016
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Digital Logic
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sourojit
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11
Frequency of output signal?
I got the ans as 1/(5*25) = 1/125. None of the, match
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Dec 18, 2016
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Digital Logic
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prasitamukherjee
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12
Clock frequency required for proper operation of ripple counter
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper operation of counter is? (A) 1 MHz (B) 500 MHz (C) 1.5 MHz (D) 2 MHz
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Oct 17, 2016
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Digital Logic
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GateAspirant999
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digital-counter
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13
Counters+Frequency
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Oct 13, 2016
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Digital Logic
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Rahul Jain25
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14
MadeEasy Test Series: CO & Architecture - Clock Frequency
Consider 1 GHz clock frequency processor, uses different operand accessing models shown below: Assume that 2 memory cycles consumed for memory reference, 3 cycles consumed for arithmetic computation and 1 cycle consumed when the operand is in ... (in million words/sec) of processor is __________ (upto 2 to decimal places).(ANSWER-344.82)
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Jan 29, 2016
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CO and Architecture
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sourav.
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clock-frequency
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15
Maximum clock frequency for the circuit
In the following digital circuit shown above, the worst case delay is of 30 nsec and the AND gate has delay of 10 nsec. The maximum clock frequency of the circuit to operate is _ MHz. I calculated as follows : ... the flip-flop delay once? The solution gives the frequency as 14.2 MHz, adding the delay due to flip-flop twice. Why?
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Jan 16, 2016
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Digital Logic
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Utk
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digital-logic
clock-frequency
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16
What is the o/p according to given timing diagram?
a) A = 0, 1, 0, 0, B = 1, 0, 1, 1 b) A = 1, 0, 1, 1, B = 0, 1, 0, 0 c) A = 1, 1, 0, 0, B = 1, 1, 0, 0 d) A = 0, 1, 0, 0, B = 0, 1, 0, 0 I thought it would be (c) as previous states should persist for 1st clock. But answer given is (a). Can somebody please explain??
asked
Dec 30, 2015
in
Digital Logic
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Tushar Shinde
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digital-logic
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clock-frequency
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17
Whether to count MegaByte as 2^20 or 10^6
The first word of the memory block (each block contains 4 words of 4 bytes each) takes 5 clock cycles and remaining 3 words are transferred in consecutive cycles. Given the clock rate is 100 MHz. The data rate (in MBps) of memory for transferring one ... Please give me reference for that ! (So I can be happy :D ) From Made Easy FLT 6-Practice Test 14 Q 61
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Dec 1, 2015
in
CO and Architecture
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Akash Kanase
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co-and-architecture
clock-frequency
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2
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18
Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of ... reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?
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Oct 27, 2015
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CO and Architecture
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khushtak
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co-and-architecture
cache-memory
clock-frequency
clock-cycles
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1
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19
Drd0 2008 q-11 ch-3 i/o interface
In an n- CPU shared bus system, if z is the probability that any CPU requests the bus in a given cycle, the probability that only one CPU uses the bus is given by- A. Nz(1-z)n-1 B. Z(1-z)n-1 C. N(1-z)n D. (N-1)z(1-z)n
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Oct 20, 2015
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CO and Architecture
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khushtak
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co-and-architecture
clock-frequency
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20
Q 37 me ch-5
A hierarical cache memory subsystem has a cache access time of 50ns and the main storage access time is of 500ns . with the read hit ratio of 0.9, what is the average access time of the system considering only memory read cycle in the write through scheme? a. 10 ns b. 100 ns c. 50ns d. 500ns
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Oct 20, 2015
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CO and Architecture
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khushtak
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cache-memory
clock-frequency
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2
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21
Made Easy CA pipeline q2
A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the throughout of the system if 20% of instructions are branch instructions ignore the ... of 4 cycles. A.55 MIPS B.45 MIPS C. 65 MIPS D. None of these. (explain the solution as well)
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Oct 20, 2015
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CO and Architecture
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khushtak
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pipelining
clock-frequency
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vote
1
answer
22
Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40
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Oct 7, 2015
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CO and Architecture
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khushtak
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clock-frequency
co-and-architecture
cisc-risc-architecture
+18
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2
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23
GATE2007-IT-36
The floating point unit of a processor using a design $D$ takes $2t$ cycles compared to $t$ cycles taken by the fixed point unit. There are two more design suggestions $D_1$ and $D_2$. $D_1$ uses $30\%$ more cycles for fixed point unit but $30\%$ less cycles for floating point unit as ... $D_j$) $D_1 > D > D_2$ $D_2 > D > D_1$ $D > D_2 > D_1$ $D > D_1 > D_2$
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Oct 30, 2014
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CO and Architecture
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Ishrat Jahan
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gate2007-it
co-and-architecture
normal
clock-frequency
+11
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1
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24
GATE1992-01-iii
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because _____
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Sep 13, 2014
in
CO and Architecture
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Kathleen
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