Recent questions tagged clock-frequency

A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ seconds. The a...

Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the...

A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the ...

An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper ...

___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.

Consider 1 GHz clock frequency processor, uses different operand accessing models shown below: Assume that 2 memory...

In the following digital circuit shown above, the worst case delay is of 30 nsec and the AND gate has delay of 10 nsec. The maximum clock frequency of the circuit to oper...

a) A = 0, 1, 0, 0, B = 1, 0, 1, 1b) A = 1, 0, 1, 1, B = 0, 1, 0, 0c) A = 1, 1, 0, 0, B = 1, 1, 0, 0d) A = 0, 1, 0, 0, B = 0, 1, 0, 0I thought it would be (c) as previous ...

suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memor...

A hierarical cache memory subsystem has a cache access time of 50ns and the main storage access time is of 500ns . with  the read hit ratio of 0.9, what is the average ac...

A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is compl...

Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because ?