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Recent questions tagged clock-frequency
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1
GATE Overflow | Mock GATE | Test 1 | Question: 60
A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ seconds. The architect has delivered that a substantial increase in clock rate is ... clock cycles as machine A for this program. What clock rate should be targeted for a best design? (In $MHz$)
Ruturaj Mohanty
asked
in
CO and Architecture
Dec 27, 2018
by
Ruturaj Mohanty
1.0k
views
go-mockgate-1
numerical-answers
clock-cycles
clock-frequency
co-and-architecture
0
votes
1
answer
2
C pipelining
4 stage pipeline with respective delays of 2 ns , 8 ns , 3 ns , 1 ns .It is enhanced to improve the performance with stages , but in the enhancement process longest delay stage is decomposed into 2 equal delays . What is the clock frequency in the enhanced pipeline? please explain a bit..
hitendra singh
asked
in
CO and Architecture
Dec 22, 2018
by
hitendra singh
579
views
co-and-architecture
pipelining
clock-frequency
0
votes
0
answers
3
TANCET 2017 CLOCK FREQUENCY
Balaji Jegan
asked
in
CO and Architecture
Oct 24, 2018
by
Balaji Jegan
164
views
tancet2017
co-and-architecture
clock-frequency
3
votes
1
answer
4
Maximum Clock Rate
Delay of AND gate = 1ns, FF = 2ns. What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
Tuhin Dutta
asked
in
Digital Logic
Jan 18, 2018
by
Tuhin Dutta
902
views
digital-logic
clock-frequency
1
vote
0
answers
5
maximum clock rate
What is the maximum clock rate possible to apply so that counter will work satisfactorily? a) 143 MHz b) 200 MHz c) 333 MHz
Tuhin Dutta
asked
in
Digital Logic
Jan 18, 2018
by
Tuhin Dutta
463
views
digital-logic
clock-frequency
0
votes
2
answers
6
Output clock frequency
Parshu gate
asked
in
Digital Logic
Dec 6, 2017
by
Parshu gate
2.2k
views
digital-logic
clock-frequency
digital-counter
0
votes
0
answers
7
MadeEasy Subject Test: CO & Architecture - Clock Frequency
I got 34 as answer, but given is 35.
rahul sharma 5
asked
in
CO and Architecture
Nov 6, 2017
by
rahul sharma 5
359
views
made-easy-test-series
co-and-architecture
clock-frequency
3
votes
1
answer
8
Test by Bikram | Mock GATE | Test 4 | Question: 51
In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of the Mod-256 counter is _____MHz.
Bikram
asked
in
Digital Logic
May 14, 2017
by
Bikram
839
views
tbb-mockgate-4
numerical-answers
digital-logic
clock-frequency
digital-counter
synchronous-asynchronous-circuits
4
votes
2
answers
9
gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?
Purple
asked
in
CO and Architecture
Feb 7, 2017
by
Purple
1.8k
views
co-and-architecture
machine-instruction
clock-frequency
4
votes
1
answer
10
gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8
Purple
asked
in
CO and Architecture
Feb 7, 2017
by
Purple
2.6k
views
machine-instruction
co-and-architecture
clock-frequency
1
vote
1
answer
11
MadeEasy Workbook: CO & Architecture - Clock Frequency
Smriti012
asked
in
CO and Architecture
Feb 1, 2017
by
Smriti012
348
views
made-easy-booklet
co-and-architecture
clock-frequency
0
votes
1
answer
12
MadeEasy Workbook: CO & Architecture - Clock Frequency
Smriti012
asked
in
CO and Architecture
Feb 1, 2017
by
Smriti012
424
views
co-and-architecture
made-easy-booklet
clock-frequency
1
vote
1
answer
13
Virtual Gate Test Series: Digital Logic - Flip Flop Delay
Sheshang
asked
in
Digital Logic
Jan 18, 2017
by
Sheshang
508
views
digital-logic
clock-frequency
flip-flop
virtual-gate-test-series
0
votes
1
answer
14
Ace Test Series: Digital Logic - Digital Counter
sourojit
asked
in
Digital Logic
Dec 24, 2016
by
sourojit
284
views
ace-test-series
digital-logic
digital-counter
clock-frequency
0
votes
2
answers
15
Frequency of output signal?
I got the ans as 1/(5*25) = 1/125. None of the, match
prasitamukherjee
asked
in
Digital Logic
Dec 18, 2016
by
prasitamukherjee
651
views
digital-logic
clock-frequency
digital-counter
2
votes
1
answer
16
Clock frequency required for proper operation of ripple counter
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper operation of counter is? (A) 1 MHz (B) 500 MHz (C) 1.5 MHz (D) 2 MHz
GateAspirant999
asked
in
Digital Logic
Oct 17, 2016
by
GateAspirant999
7.9k
views
digital-logic
clock-frequency
digital-counter
9
votes
1
answer
17
Counters+Frequency
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
Rahul Jain25
asked
in
Digital Logic
Oct 13, 2016
by
Rahul Jain25
6.7k
views
digital-logic
digital-counter
clock-frequency
1
vote
1
answer
18
MadeEasy Test Series: CO & Architecture - Clock Frequency
Consider 1 GHz clock frequency processor, uses different operand accessing models shown below: Assume that 2 memory cycles consumed for memory reference, 3 cycles consumed for arithmetic computation and 1 cycle consumed when the operand is in ... (in million words/sec) of processor is __________ (upto 2 to decimal places).(ANSWER-344.82)
sourav.
asked
in
CO and Architecture
Jan 29, 2016
by
sourav.
1.3k
views
made-easy-test-series
co-and-architecture
clock-frequency
1
vote
1
answer
19
Maximum clock frequency for the circuit
In the following digital circuit shown above, the worst case delay is of 30 nsec and the AND gate has delay of 10 nsec. The maximum clock frequency of the circuit to operate is _ MHz. I calculated as follows : ... the flip-flop delay once? The solution gives the frequency as 14.2 MHz, adding the delay due to flip-flop twice. Why?
Utk
asked
in
Digital Logic
Jan 16, 2016
by
Utk
2.9k
views
digital-logic
clock-frequency
1
vote
1
answer
20
What is the o/p according to given timing diagram?
a) A = 0, 1, 0, 0, B = 1, 0, 1, 1 b) A = 1, 0, 1, 1, B = 0, 1, 0, 0 c) A = 1, 1, 0, 0, B = 1, 1, 0, 0 d) A = 0, 1, 0, 0, B = 0, 1, 0, 0 I thought it would be (c) as previous states should persist for 1st clock. But answer given is (a). Can somebody please explain??
Tushar Shinde
asked
in
Digital Logic
Dec 30, 2015
by
Tushar Shinde
794
views
digital-logic
flip-flop
clock-frequency
1
vote
1
answer
21
Whether to count MegaByte as 2^20 or 10^6
The first word of the memory block (each block contains 4 words of 4 bytes each) takes 5 clock cycles and remaining 3 words are transferred in consecutive cycles. Given the clock rate is 100 MHz. The data rate (in MBps) of memory for transferring one ... Please give me reference for that ! (So I can be happy :D ) From Made Easy FLT 6-Practice Test 14 Q 61
Akash Kanase
asked
in
CO and Architecture
Dec 1, 2015
by
Akash Kanase
614
views
co-and-architecture
clock-frequency
6
votes
2
answers
22
Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of ... reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?
khushtak
asked
in
CO and Architecture
Oct 27, 2015
by
khushtak
12.2k
views
co-and-architecture
cache-memory
clock-frequency
clock-cycles
4
votes
1
answer
23
Drd0 2008 q-11 ch-3 i/o interface
In an n- CPU shared bus system, if z is the probability that any CPU requests the bus in a given cycle, the probability that only one CPU uses the bus is given by- A. Nz(1-z)n-1 B. Z(1-z)n-1 C. N(1-z)n D. (N-1)z(1-z)n
khushtak
asked
in
CO and Architecture
Oct 20, 2015
by
khushtak
1.1k
views
co-and-architecture
clock-frequency
2
votes
1
answer
24
Q 37 me ch-5
A hierarical cache memory subsystem has a cache access time of 50ns and the main storage access time is of 500ns . with the read hit ratio of 0.9, what is the average access time of the system considering only memory read cycle in the write through scheme? a. 10 ns b. 100 ns c. 50ns d. 500ns
khushtak
asked
in
CO and Architecture
Oct 20, 2015
by
khushtak
547
views
co-and-architecture
cache-memory
clock-frequency
7
votes
2
answers
25
Made Easy CA pipeline q2
A 5-stage pipeline is used to overlap all the instructions except the branch instructions. The target of the branch can't be fetched till the current instruction is completed. What is the throughout of the system if 20% of instructions are branch instructions ignore the ... of 4 cycles. A.55 MIPS B.45 MIPS C. 65 MIPS D. None of these. (explain the solution as well)
khushtak
asked
in
CO and Architecture
Oct 20, 2015
by
khushtak
3.1k
views
co-and-architecture
pipelining
clock-frequency
2
votes
2
answers
26
Q-20 (control unit design) madeEasy workBook 2015
Show below are sements of a code run on a CISC and RISC archy separately CISC RISC MOV AX,05 MOV AX,00 MOV BX,06 MOV BX,05 MUL AX,BX MOV CX,06 start:ADD AX,BX loop loop start; loop till CX=0 If the MUL instruction takes 40 clock cycles, ... 2.8 (c) The CISC code runs slower by a factor of 0.025 (d) The RISC code will run faster by a factor of 40
khushtak
asked
in
CO and Architecture
Oct 7, 2015
by
khushtak
2.1k
views
clock-frequency
co-and-architecture
cisc-risc-architecture
31
votes
2
answers
27
GATE IT 2007 | Question: 36
The floating point unit of a processor using a design $D$ takes $2t$ cycles compared to $t$ cycles taken by the fixed point unit. There are two more design suggestions $D_1$ and $D_2$. $D_1$ uses $30\%$ more cycles for fixed point unit but $30\%$ less cycles for floating ... $D_1 > D > D_2$ $D_2 > D > D_1$ $D > D_2 > D_1$ $D > D_1 > D_2$
Ishrat Jahan
asked
in
CO and Architecture
Oct 30, 2014
by
Ishrat Jahan
5.7k
views
gateit-2007
co-and-architecture
normal
clock-frequency
19
votes
2
answers
28
GATE CSE 1992 | Question: 01-iii
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because _____
Kathleen
asked
in
CO and Architecture
Sep 13, 2014
by
Kathleen
2.3k
views
gate1992
normal
co-and-architecture
clock-frequency
fill-in-the-blanks
11
votes
1
answer
29
Clock-frequency
Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because ?
srinath
asked
in
CO and Architecture
Sep 3, 2014
by
srinath
1.9k
views
co-and-architecture
clock-frequency
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