MadeEasy Workbook: CO & Architecture - Clock Frequency

Question

Common Data Questions (8 and 9):
Consider an accumulator-based CPU supports only single address instruction. The CPU supports the following instructions.
LOAD A : Load A from memory into accumulator AC. STORE A : Store contents of accumulator AC in memory location M.
ADD B : Load B into data register (DR) and add to accumulator.
MOVE A, $B$ : Move content of $B$ to $A$.
SUB A, B : Subtract B from A:
Q. 8 Assume CPU uses the memory referencing and each instruction LOAD, STORE and ADD takes one clock cycle. To compute $Z=X+Y C P U$ takes how many minimum number of clock cycles?
(a) 2
(b) 3
(c) 4
(d) 5
Q. 9 How many minimum clock cycles are needed when accumulator becomes O . If each instruction takes one clock cycles?

• A. 0
  
• B. 1
  
• C. 2
  
• D. 3

Answer 1

Q8)

LOAD X

ADD Y

STORE Z

So answer should be 3.

Comments

Q9??

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yup!! Mainly 9th was my question... I knew Q8.....Unable to get what is asked in Q9..

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Yes!! answer is 3 for Q8!