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Recent questions tagged clock-cycles
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Design a Asynchronous Up counter that start it’s counting from zero and ends at 11 and again starts from zero. Draw the output status of all Flip Flops after every clock. How many clocks are required to reach 11?
M.Zain
305
views
M.Zain
asked
Dec 30, 2022
Digital Logic
digital-logic
clock-cycles
flip-flop
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–
1
votes
1
answer
2
DRDO CSE 2022 Paper 2 | Question: 4
A system $\mathrm{X}$ with $2 \mathrm{~GHz}$ clock speed runs a program in $10$ seconds. We want to build a system $\mathrm{Y}$ to run the same program in $6$ seconds. For this, system $\mathrm{Y}$ needs $1.2$ times as many clock cycles as system $\mathrm{X}$. What should be the clock speed of the system $\mathrm{Y}?$
A system $\mathrm{X}$ with $2 \mathrm{~GHz}$ clock speed runs a program in $10$ seconds. We want to build a system $\mathrm{Y}$ to run the same program in $6$ seconds. Fo...
admin
378
views
admin
asked
Dec 15, 2022
CO and Architecture
drdocse-2022-paper2
co-and-architecture
clock-cycles
5-marks
descriptive
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–
0
votes
1
answer
3
cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and accessing of the cache memory required 2 clock cycles. If cache miss rate is 2%, then the effective CPI for the system with the cache is ____.
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and acc...
someshawasthi
369
views
someshawasthi
asked
Nov 17, 2022
CO and Architecture
cache-memory
clock-cycles
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–
0
votes
0
answers
4
How many cycle per second are spent on I/O if polling is used with Interrupts?
Manpreet Saluja
215
views
Manpreet Saluja
asked
Nov 7, 2022
Computer Networks
co-and-architecture
clock-cycles
input-output
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–
0
votes
1
answer
5
SelfDoubt
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
someshawasthi
356
views
someshawasthi
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
self-doubt
machine-instruction
clock-cycles
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–
1
votes
2
answers
6
GATE Overflow | Mock GATE | Test 1 | Question: 60
A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ seconds. The architect has delivered that a substantial increase in clock rate is ... clock cycles as machine A for this program. What clock rate should be targeted for a best design? (In $MHz$)
A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ seconds. The a...
Ruturaj Mohanty
1.1k
views
Ruturaj Mohanty
asked
Dec 27, 2018
CO and Architecture
go-mockgate-1
numerical-answers
clock-cycles
clock-frequency
co-and-architecture
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–
2
votes
1
answer
7
pipelining
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 25% of the time for 1 cycle and 10% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI ?(ans=2.05)
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay. The p...
Satbir
1.5k
views
Satbir
asked
Dec 7, 2018
CO and Architecture
pipelining
co-and-architecture
clock-cycles
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2
votes
2
answers
8
Pipelining
Na462
2.1k
views
Na462
asked
Nov 7, 2018
CO and Architecture
pipelining
co-and-architecture
clock-cycles
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–
0
votes
1
answer
9
Computer organization
How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time? (a) 10^9 cycles (b) 50 × 10^7 cycles (c) 10^8 cycles (d) 50 cycles Solution: Option (b)
How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time?(a) 10^9 cycles (b) 50 × 10^7 cycles (c) 10^8 cycles (d) 5...
sahil_malik
3.8k
views
sahil_malik
asked
Oct 10, 2018
CO and Architecture
co-and-architecture
clock-cycles
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–
0
votes
0
answers
10
ME test series
newdreamz a1-z0
371
views
newdreamz a1-z0
asked
Oct 7, 2018
CO and Architecture
co-and-architecture
machine-instruction
operand-forwarding
clock-cycles
numerical-answers
made-easy-test-series
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–
3
votes
1
answer
11
Minimum clock cycle
Na462
1.6k
views
Na462
asked
Sep 24, 2018
CO and Architecture
co-and-architecture
pipelining
clock-cycles
numerical-answers
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–
0
votes
0
answers
12
Computer organisation- DMA
sidlewis
228
views
sidlewis
asked
Sep 12, 2018
CO and Architecture
co-and-architecture
cache-memory
array
clock-cycles
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–
0
votes
1
answer
13
Pipelining
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which takes 1 clock period. In a pipelined execution of a 5-step task, a new instruction is read and ... the speedup ratio of pipe line processing system over an equivalent non pipeline processing system is ________. Ans. 4.8 Please Explain Briefly
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which takes 1 clock period. I...
Na462
1.5k
views
Na462
asked
Jul 21, 2018
CO and Architecture
pipelining
co-and-architecture
speedup
clock-cycles
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–
1
votes
1
answer
14
Addressing mode
Prateek Raghuvanshi
1.1k
views
Prateek Raghuvanshi
asked
May 27, 2018
CO and Architecture
addressing-modes
clock-cycles
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–
1
votes
1
answer
15
made easy test series
rohit vishkarma
392
views
rohit vishkarma
asked
Jan 4, 2018
Digital Logic
combinational-circuit
clock-cycles
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–
2
votes
1
answer
16
Pipelining
Parshu gate
576
views
Parshu gate
asked
Nov 29, 2017
CO and Architecture
pipelining
co-and-architecture
clock-cycles
speedup
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–
2
votes
1
answer
17
Pipelining Problem
How to slove this type of problems? How to understand the problem?Please help me out. Given answer is 31
How to slove this type of problems? How to understand the problem?Please help me out. Given answer is 31
Parshu gate
1.4k
views
Parshu gate
asked
Nov 18, 2017
CO and Architecture
pipelining
co-and-architecture
clock-cycles
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–
4
votes
1
answer
18
Test question on Pipelining
Parshu gate
1.4k
views
Parshu gate
asked
Nov 3, 2017
CO and Architecture
co-and-architecture
pipelining
clock-cycles
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–
0
votes
1
answer
19
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 19
In an $8$ segment pipeline, the total number of clock pulses that process $150$ tasks are ______ cycles.
In an $8$ segment pipeline, the total number of clock pulses that process $150$ tasks are ______ cycles.
Bikram
239
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
clock-cycles
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–
1
votes
1
answer
20
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 2
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment pipeline is _______ cycles.
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment...
Bikram
387
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
pipelining
clock-cycles
+
–
6
votes
2
answers
21
Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of ... reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memor...
khushtak
12.4k
views
khushtak
asked
Oct 27, 2015
CO and Architecture
co-and-architecture
cache-memory
clock-frequency
clock-cycles
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