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Recent questions tagged cpu

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Best Open Video Playlist for CPU and I/O Scheduling Topic | Operating Systems
Please list out the best free available video playlist for CPU and I/O Scheduling from Operating Systems as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO ... standard ones are more likely to be selected as best. For the full list of selected videos please see here

makhdoom ghaya asked in Study Resources Aug 20, 2022

by makhdoom ghaya

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1 vote

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Applied Mock Test
A uniprocessor computer system has three processes, which alternate 20ms CPU bursts with 80ms I/O bursts. All the processes were created at nearly the same time. The I/O of all the processes can proceed in parallel. The absolute difference of CPU utilization (over a long period of time) using FCFS and Round Robin (time quantum 10ms) for this system is _____ %

LRU asked in Operating System Dec 14, 2021

by LRU

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CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

Devshree Dubey asked in CO and Architecture Mar 20, 2019

by Devshree Dubey

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Cpu time
Find CPU time of computer with 500 MHz and following class distribution for program with 100 instructions. Class CPI Frequency 1 3 40% 2 5 20% 3 3 30% 4 1 10% Ans: 640ns

Alina asked in CO and Architecture Jan 3, 2019

by Alina

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TANCET 2016 COA

Balaji Jegan asked in CO and Architecture Oct 23, 2018

by Balaji Jegan

91 views

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0 answers

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Self doubt CO
Say the processor runs at 600 MHz then what is CPU clock time?

iarnav asked in CO and Architecture Oct 3, 2018

by iarnav

198 views

1 vote

0 answers

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Cpu performance related question, In one of the standard book named Patterson
I am confused whether to count the IPC given in the question or not as Each binary is running for same number of cycles why to count them, please provide a solution with some discussion for this question . @arjun Suresh sir.

karan0908 asked in CO and Architecture Aug 23, 2018

265 views

1 vote

1 answer

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Instruction or Operand Fetch
Consider the following μ-program? Which of the following operation is performed by above μ-program? A. Instruction fetch B. Direct operand fetch C. Interrupt sub program initiation D. Indirect operand fetch. Ans. B Please Specify proper reason. My Doubt is in option B and D why D isnt the answer ?

Na462 asked in CO and Architecture Jul 31, 2018

by Na462

836 views

1 vote

0 answers

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How to draw conclusion from given statements?
What is the conclusion that can be drawn from the following statements, 1) CPU utilization = 15%. 2) Hard Disk utilization = 95%. 3) Other I/O devices = 5%.

AnilGoudar asked in Operating System Jan 2, 2018

123 views

2 votes

2 answers

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Micro Instruction
Conditional bit(Flag) Micro-opn. Next Address Micro-Instruction Format If a micro program supports 46μ operations with a parallelism of 2,how many and what size of field exists in micro operation field? Given size of micro-opn field is 9bits. Answer: Total 9 bis divided in 4 and 5 bit. Can anyone explain how this division is being done.

Sourajit25 asked in CO and Architecture Nov 25, 2017

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Random
Can I/O bound and CPU bound activities happen at the same time (overlapping) ?

Warlock lord asked in Operating System Nov 9, 2017

by Warlock lord

199 views

1 vote

1 answer

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Test by Bikram | Mock GATE | Test 2 | Question: 49
Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand, operates on them, and then pushes the result back onto the stack. Push b Push x Add ... of execution, the stack is empty. I and III only II and III only II only I, II, and III

Bikram asked in GATE Jan 24, 2017

by Bikram

395 views

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Can any one provide a chart of comparison of various cpu scheuling algorithms in operating system?

sidlewis asked in Operating System Oct 25, 2016

200 views

2 votes

2 answers

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UGC NET CSE | December 2011 | Part 2 | Question: 31
CPU does not perform the operation Data transfer Logic operation Arithmetic operation All of the above

makhdoom ghaya asked in CO and Architecture Aug 20, 2016

by makhdoom ghaya

3.0k views

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Hardware Operation Chart of one digital system, anyone can help?
I try to figure out one of the tests that adopted from GATE exams, but nothing founds, anyone can describe it for me? Question: We shown the Hardware Operation Chart of one digital system in the following figure: activity of control signals for each operational ... unit how many and, or gate is needed? A) 4, 5 B) 4, 4 C) 5,3 D)4, 3

Sara Nimlon asked in CO and Architecture Jul 1, 2016

581 views

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3 answers

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Surprised Nano Memory (VERTICAL Micro Instruction) Reduced bits?!
Hi to all, This is an Challenging Interview Question that I see lots of this example in GATE Exams. In a digital system with micro-programmed control circuit, We have 32 Control Signal and total distinct pattern is 450. if the micro-programmed ... to 23kbits but the solution is (a). (i.e 22K bits). any EXPERT can say why 22K is true?

asambeladi asked in CO and Architecture Jun 17, 2016

2.0k views

1 vote

1 answer

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Vertical Instruction in Control MEmory?
In a digital system we have 120 control signals.In Operating Chart of this system (ASM Chart) we have 8 distinct condition. with inspecting the activity of micro operation shows we have reduced control memory bits with vertical micro instruction (nano memory ... *120 3- in size of micro memory we can saved 2^10*110 Who can help in this previous exam question.

DrMhmd asked in CO and Architecture May 13, 2016

by DrMhmd

1.3k views

0 votes

2 answers

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I am reading Galvin O.S. and came across the given below line. please tell me where am I wrong?
I am reading Galvin O.S. and came across this line 2. When a process switches from the running state to the ready state (for example, when an interrupt occurs), scheduling is not needed I but If a ... moved to ready queue scheduling is definitely needed. Where am I wrong? O.S. Galvin Edition 9th Page 264

Shivam Chauhan asked in Operating System May 5, 2016

by Shivam Chauhan

398 views

0 votes

1 answer

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Cpu operand fetch speed
How many cycles here indexed addressing mode will take?

Pradip Nichite asked in CO and Architecture Jan 14, 2016

by Pradip Nichite

203 views

4 votes

6 answers

20

ISRO2011-41
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will be $2$ $4$ $8$ $16$

ajit asked in CO and Architecture Oct 1, 2015

by ajit

4.7k views

5 votes

1 answer

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ISRO2014-10
The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is ______ $1$ $2$ $8$ $16$

ajit asked in CO and Architecture Sep 8, 2015

by ajit

5.0k views

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