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Recent questions tagged cpu
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Andrew S. Tanenbaum - Modern Operating Systems
Measurements of a certain system have shown that the average process runs for a time T before blocking on I/O. A process switch requires a time S, which is effectively wasted (overhead). For round-robin scheduling with quantum Q, giv e a formula for the CPU efficiency for each of the ... ) Q = ∞ (b) Q > T (c) S < Q < T (d) Q = S (e) Q nearly 0
Measurements of a certain system have shown that the average process runs for a time T before blocking on I/O. A process switch requires a time S, which is effectively wa...
arjunwkb
359
views
arjunwkb
asked
Feb 15, 2023
Operating System
operating-system
cpu
input-output
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0
votes
0
answers
2
Best Open Video Playlist for CPU and I/O Scheduling Topic | Operating Systems
Please list out the best free available video playlist for CPU and I/O Scheduling from Operating Systems as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO ... standard ones are more likely to be selected as best. For the full list of selected videos please see here
Please list out the best free available video playlist for CPU and I/O Scheduling from Operating Systems as an answer here (only one playlist per answer). We'll then sele...
makhdoom ghaya
258
views
makhdoom ghaya
asked
Aug 20, 2022
Study Resources
go-classroom
missing-videos
free-videos
video-links
cpu
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1
votes
0
answers
3
Applied Mock Test
A uniprocessor computer system has three processes, which alternate 20ms CPU bursts with 80ms I/O bursts. All the processes were created at nearly the same time. The I/O of all the processes can proceed in parallel. The absolute difference of CPU utilization (over a long period of time) using FCFS and Round Robin (time quantum 10ms) for this system is _____ %
A uniprocessor computer system has three processes, which alternate 20ms CPU bursts with 80ms I/O bursts. All the processes were created at nearly the same time. The I/O ...
LRU
386
views
LRU
asked
Dec 14, 2021
Operating System
test-series
operating-system
cpu
process-scheduling
process
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–
0
votes
0
answers
4
CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.
Please can anyone help me how to measure the CPU Performance and everything related with it.
Devshree Dubey
503
views
Devshree Dubey
asked
Mar 19, 2019
CO and Architecture
cpu
co-and-architecture
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–
0
votes
0
answers
5
Cpu time
Find CPU time of computer with 500 MHz and following class distribution for program with 100 instructions. Class CPI Frequency 1 3 40% 2 5 20% 3 3 30% 4 1 10% Ans: 640ns
Find CPU time of computer with 500 MHz and following class distribution for program with 100 instructions.Class CPI Frequency1 3 40%2 ...
Alina
491
views
Alina
asked
Jan 3, 2019
CO and Architecture
co-and-architecture
cpu
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0
votes
0
answers
6
TANCET 2016 COA
Balaji Jegan
158
views
Balaji Jegan
asked
Oct 23, 2018
CO and Architecture
tancet2016
co-and-architecture
cpu
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0
votes
0
answers
7
Self doubt CO
Say the processor runs at 600 MHz then what is CPU clock time?
Say the processor runs at 600 MHz then what is CPU clock time?
iarnav
431
views
iarnav
asked
Oct 3, 2018
CO and Architecture
co-and-architecture
cpu
clock-time
self-doubt
numerical-answers
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–
1
votes
0
answers
8
Cpu performance related question, In one of the standard book named Patterson
I am confused whether to count the IPC given in the question or not as Each binary is running for same number of cycles why to count them, please provide a solution with some discussion for this question . @arjun Suresh sir.
I am confused whether to count the IPC given in the question or not as Each binary is running for same number of cycles why to count them, please provide a solution with ...
karan0908
326
views
karan0908
asked
Aug 23, 2018
CO and Architecture
cpu
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–
1
votes
1
answer
9
Instruction or Operand Fetch
Consider the following μ-program? Which of the following operation is performed by above μ-program? A. Instruction fetch B. Direct operand fetch C. Interrupt sub program initiation D. Indirect operand fetch. Ans. B Please Specify proper reason. My Doubt is in option B and D why D isnt the answer ?
Consider the following μ-program? Which of the following operation is performed by above μ-program?A. Instruction fetchB. Direct operand fetchC. Interrupt sub progra...
Na462
976
views
Na462
asked
Jul 31, 2018
CO and Architecture
co-and-architecture
cpu
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–
1
votes
0
answers
10
How to draw conclusion from given statements?
What is the conclusion that can be drawn from the following statements, 1) CPU utilization = 15%. 2) Hard Disk utilization = 95%. 3) Other I/O devices = 5%.
What is the conclusion that can be drawn from the following statements,1) CPU utilization = 15%.2) Hard Disk utilization = 95%.3) Other I/O devices = 5%.
AnilGoudar
200
views
AnilGoudar
asked
Jan 2, 2018
Operating System
operating-system
cpu
+
–
2
votes
2
answers
11
Micro Instruction
Conditional bit(Flag) Micro-opn. Next Address Micro-Instruction Format If a micro program supports 46μ operations with a parallelism of 2,how many and what size of field exists in micro operation field? Given size of micro-opn field is 9bits. Answer: Total 9 bis divided in 4 and 5 bit. Can anyone explain how this division is being done.
Conditional bit(Flag)Micro-opn.Next Address Micro-Instruction FormatIf a micro program supports 46μ operations with a parallel...
Sourajit25
2.4k
views
Sourajit25
asked
Nov 24, 2017
CO and Architecture
microprogramming
co-and-architecture
control-unit
cpu
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0
votes
0
answers
12
Random
Can I/O bound and CPU bound activities happen at the same time (overlapping) ?
Can I/O bound and CPU bound activities happen at the same time (overlapping) ?
Warlock lord
424
views
Warlock lord
asked
Nov 9, 2017
Operating System
cpu
+
–
1
votes
1
answer
13
Test by Bikram | Mock GATE | Test 2 | Question: 49
Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand, operates on them, and then pushes the result back onto the stack. Push b Push x Add ... of execution, the stack is empty. I and III only II and III only II only I, II, and III
Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand,...
Bikram
887
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cpu
machine-instruction
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–
0
votes
0
answers
14
Can any one provide a chart of comparison of various cpu scheuling algorithms in operating system?
sidlewis
256
views
sidlewis
asked
Oct 25, 2016
Operating System
operating-system
cpu
+
–
2
votes
2
answers
15
UGC NET CSE | December 2011 | Part 2 | Question: 31
CPU does not perform the operation Data transfer Logic operation Arithmetic operation All of the above
CPU does not perform the operationData transferLogic operationArithmetic operationAll of the above
makhdoom ghaya
3.5k
views
makhdoom ghaya
asked
Aug 19, 2016
CO and Architecture
ugcnetcse-dec2011-paper2
co-and-architecture
cpu
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–
0
votes
0
answers
16
Hardware Operation Chart of one digital system, anyone can help?
I try to figure out one of the tests that adopted from GATE exams, but nothing founds, anyone can describe it for me? Question: We shown the Hardware Operation Chart of one digital system in the following figure: activity of control signals for each operational ... unit how many and, or gate is needed? A) 4, 5 B) 4, 4 C) 5,3 D)4, 3
I try to figure out one of the tests that adopted from GATE exams, but nothing founds, anyone can describe it for me?Question: We shown the Hardware Operation Chart of on...
Sara Nimlon
864
views
Sara Nimlon
asked
Jun 30, 2016
CO and Architecture
digital-logic
co-and-architecture
control-unit
cpu
microprogramming
non-gate
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–
0
votes
3
answers
17
Surprised Nano Memory (VERTICAL Micro Instruction) Reduced bits?!
Hi to all, This is an Challenging Interview Question that I see lots of this example in GATE Exams. In a digital system with micro-programmed control circuit, We have 32 Control Signal and total distinct pattern is 450. if the micro-programmed ... to 23kbits but the solution is (a). (i.e 22K bits). any EXPERT can say why 22K is true?
Hi to all, This is an Challenging Interview Question that I see lots of this example in GATE Exams. In a digital system with micro-programmed control circuit, We have 32...
asambeladi
2.7k
views
asambeladi
asked
Jun 16, 2016
CO and Architecture
co-and-architecture
cpu
control-unit
microprogramming
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–
1
votes
1
answer
18
Vertical Instruction in Control MEmory?
In a digital system we have 120 control signals.In Operating Chart of this system (ASM Chart) we have 8 distinct condition. with inspecting the activity of micro operation shows we have reduced control memory bits with vertical micro instruction (nano memory ... *120 3- in size of micro memory we can saved 2^10*110 Who can help in this previous exam question.
In a digital system we have 120 control signals.In Operating Chart of this system (ASM Chart) we have 8 distinct condition. with inspecting the activity of micro operatio...
DrMhmd
1.6k
views
DrMhmd
asked
May 13, 2016
CO and Architecture
co-and-architecture
control-unit
microprogramming
cpu
+
–
0
votes
2
answers
19
I am reading Galvin O.S. and came across the given below line. please tell me where am I wrong?
I am reading Galvin O.S. and came across this line 2. When a process switches from the running state to the ready state (for example, when an interrupt occurs), scheduling is not needed I but If a ... moved to ready queue scheduling is definitely needed. Where am I wrong? O.S. Galvin Edition 9th Page 264
I am reading Galvin O.S. and came across this line 2. When a process switches from the running state to the ready state (for example, when an interrupt occurs), schedulin...
Shivam Chauhan
611
views
Shivam Chauhan
asked
May 5, 2016
Operating System
cpu
process-scheduling
+
–
0
votes
1
answer
20
Cpu operand fetch speed
How many cycles here indexed addressing mode will take?
How many cycles here indexed addressing mode will take?
Pradip Nichite
344
views
Pradip Nichite
asked
Jan 14, 2016
CO and Architecture
co-and-architecture
cpu
+
–
4
votes
6
answers
21
ISRO2011-41
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will be $2$ $4$ $8$ $16$
If a microcomputer operates at $5$ MHz with an $8$-bit bus and a newer version operates at $20$ MHz with a $32$-bit bus, the maximum speed-up possible approximately will ...
ajit
5.8k
views
ajit
asked
Oct 1, 2015
CO and Architecture
isro2011
co-and-architecture
cpu
+
–
6
votes
1
answer
22
ISRO2014-10
The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is ______ $1$ $2$ $8$ $16$
The number of logical CPUs in a computer having two physical quad-core chips with hyper threading enabled is ______$1$$2$$8$$16$
ajit
5.4k
views
ajit
asked
Sep 8, 2015
CO and Architecture
co-and-architecture
isro2014
cpu
non-gate
+
–
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