Recent questions tagged cpu

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CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20 in CO and Architecture by Devshree Dubey Boss (13.7k points) | 34 views

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Cpu time
Find CPU time of computer with 500 MHz and following class distribution for program with 100 instructions. Class CPI Frequency 1 3 40% 2 5 20% 3 3 30% 4 1 10% Ans: 640ns

asked Jan 3 in CO and Architecture by Alina (9 points) | 42 views

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Self doubt CO
Say the processor runs at 600 MHz then what is CPU clock time?

asked Oct 3, 2018 in CO and Architecture by iarnav Loyal (8.2k points) | 40 views

+1 vote

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Cpu performance related question, In one of the standard book named Patterson
I am confused whether to count the IPC given in the question or not as Each binary is running for same number of cycles why to count them, please provide a solution with some discussion for this question . @arjun Suresh sir.

asked Aug 23, 2018 in CO and Architecture by karan0908 (83 points) | 43 views

+1 vote

1 answer

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Instruction or Operand Fetch
Consider the following μ-program? Which of the following operation is performed by above μ-program? A. Instruction fetch B. Direct operand fetch C. Interrupt sub program initiation D. Indirect operand fetch. Ans. B Please Specify proper reason. My Doubt is in option B and D why D isnt the answer ?

asked Jul 31, 2018 in CO and Architecture by Na462 Loyal (6.8k points) | 73 views

+1 vote

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How to draw conclusion from given statements?
What is the conclusion that can be drawn from the following statements, 1) CPU utilization = 15%. 2) Hard Disk utilization = 95%. 3) Other I/O devices = 5%.

asked Jan 2, 2018 in Operating System by AnilGoudar Active (4.3k points) | 35 views

+1 vote

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Micro Instruction
Conditional bit(Flag) Micro-opn. Next Address Micro-Instruction Format If a micro program supports 46μ operations with a parallelism of 2,how many and what size of field exists in micro operation field? Given size of micro-opn field is 9bits. Answer: Total 9 bis divided in 4 and 5 bit. Can anyone explain how this division is being done.

asked Nov 25, 2017 in CO and Architecture by Sourajit25 Active (1.2k points) | 530 views

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Random
Can I/O bound and CPU bound activities happen at the same time (overlapping) ?

asked Nov 9, 2017 in Operating System by Warlock lord Active (3.3k points) | 40 views

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Can any one provide a chart of comparison of various cpu scheuling algorithms in operating system?

asked Oct 25, 2016 in Operating System by sidlewis Junior (877 points) | 84 views

+2 votes

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UGCNET-Dec2011-II-31
CPU does not perform the operation Data transfer Logic operation Arithmetic operation All of the above

asked Aug 20, 2016 in CO and Architecture by makhdoom ghaya Boss (29.9k points) | 1.1k views

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Hardware Operation Chart of one digital system, anyone can help?
I try to figure out one of the tests that adopted from GATE exams, but nothing founds, anyone can describe it for me? Question: We shown the Hardware Operation Chart of one digital system in the following figure: activity of control signals for each operational ... unit how many and, or gate is needed? A) 4, 5 B) 4, 4 C) 5,3 D)4, 3

asked Jul 1, 2016 in CO and Architecture by Sara Nimlon (141 points) | 239 views

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Surprised Nano Memory (VERTICAL Micro Instruction) Reduced bits?!
Hi to all, This is an Challenging Interview Question that I see lots of this example in GATE Exams. In a digital system with micro-programmed control circuit, We have 32 Control Signal and total distinct pattern is 450. if the micro-programmed ... to 23kbits but the solution is (a). (i.e 22K bits). any EXPERT can say why 22K is true?

asked Jun 17, 2016 in CO and Architecture by asambeladi (97 points) | 702 views

+1 vote

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Vertical Instruction in Control MEmory?
In a digital system we have 120 control signals.In Operating Chart of this system (ASM Chart) we have 8 distinct condition. with inspecting the activity of micro operation shows we have reduced control memory bits with vertical micro instruction (nano memory ... *120 3- in size of micro memory we can saved 2^10*110 Who can help in this previous exam question.

asked May 13, 2016 in CO and Architecture by DrMhmd (43 points) | 647 views

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14

I am reading Galvin O.S. and came across the given below line. please tell me where am I wrong?

asked May 5, 2016 in Operating System by Shivam Chauhan Loyal (8.8k points) | 203 views

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Cpu operand fetch speed
How many cycles here indexed addressing mode will take?

asked Jan 14, 2016 in CO and Architecture by Pradip Nichite Active (1k points) | 77 views

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