1 1 vote Consider an unpipelined machine with 10nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are: $40 \%, 20 \%$ and $40 \%$, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered. 1. $2$ times 2. $4$ times 3. $6$ times 4. $8$ times (Option $1[39329]) 1$ (Option $2[39330]) 2$ (Option $3[39331]$ ) 3 (Option $4[39332]) 4$ Answer Given by Candidate : $1$ CO & Architecture ugcnetcse-dec2022 co-and-architecture pipelining speedup performance-measurement clock-cycles processing-time pipeline-stalling + – admin 777 views answer comment Share Follow Print 0 reply Please log in or register to add a comment.
0 0 votes https://www.youtube.com/watch?v=cMYCJNWVT4M spongebob answered Jan 20 spongebob comment Share Follow 0 reply Please log in or register to add a comment.