Recent questions tagged hit-ratio / GATE Overflow for GATE CSE

5 votes

1 answer

1

GO Classes Test Series 2023 | CO and Architecture | Test 3 | Question: 2
If a memory system consists of a single external cache with an access time of $20$ ns and a hit rate of $0.92,$ and a main memory with an access time of $60$ ns, what is the effective memory access time, in ns, of this system?

If a memory system consists of a single external cache with an access time of $20$ ns and a hit rate of $0.92,$ and a main memory with an access time of $60$ ns, what is ...

GO Classes

352 views

GO Classes asked Aug 31, 2022

0 votes

1 answer

2

Accesing time
Could you please differentiate below . Memory access time .hit time . search time ?? Arey yar some one answer this.. why so dumb

Could you please differentiate below. Memory access time.hit time. search time??Arey yar some one answer this.. why so dumb

Subbu.

190 views

Subbu. asked Aug 6, 2022

1 votes

1 answer

3

Applied Practice test
Suppose: TLB lookup time = 20 ns TLB hit ratio = 80% Memory access time = 75 ns PFST = 500,000 ns 50% of the pages are dirty OS uses a single level page table What is the approximated effective access time (EAT) if we assume the page fault rate is 10%? Assume the cost to update the TLB, the page table, and the frame table (if needed) is negligible.

Suppose: TLB lookup time = 20 nsTLB hit ratio = 80%Memory access time = 75 nsPFST = 500,000 ns50% of the pages are dirtyOS uses a single level page tableWhat is the appro...

darshak_devani

845 views

darshak_devani asked Oct 18, 2021

0 votes

1 answer

4

Self-doubt
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)

How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)

Anuranjan

253 views

Anuranjan asked Mar 17, 2019

0 votes

0 answers

5

effective memory access time
A demand paging uses a TLB and a single level page table stored in main memory. The memory access time is 5s. The page fault service time is 25s. If 70% of access is in TLB and of the remaining, 20% is not present in the main memory. The effective memory access time is? Thanks!

A demand paging uses a TLB and a single level page table stored in main memory. The memory access time is 5s. The page fault service time is 25s. If 70% of access is in T...

Abhipsa

1.2k views

Abhipsa asked Jan 27, 2019

2 votes

1 answer

6

TLB hit ration and memory lookup time
Consider a system where TLB lookup time is $25$ ns and memory access time is $200$ ns, respectively. Assuming a virtual address space of $2$ KB, page size of $32$ bytes, and a PTE size of $2$ bytes, what is the minimum TLB hit ratio that results in an average v2p (virtual to physical) translation latency of $185$ ns?

Consider a system where TLB lookup time is $25$ ns and memory access time is $200$ ns, respectively. Assuming a virtual address space of $2$ KB, page size of $32$ bytes, ...

dd

770 views

dd asked Jan 13, 2019

0 votes

0 answers

7

CO madeeasy 2019 Multi level cache
please explain how hit ratio of L2 is taken as 0.5? instead of 0.9 as 10 misses are mentioned is it like as 20 misses at levle 1 out of which only 10 missed at level 2, so 10 out of 20 (and not 100) hence 0.5?

please explain how hit ratio of L2 is taken as 0.5? instead of 0.9 as 10 misses are mentionedis it like as 20 misses at levle 1 out of which only 10 missed at level 2, so...

Markzuck

531 views

Markzuck asked Dec 21, 2018

0 votes

1 answer

8

TLB OS
Why the formula used here is not P(10) + (1-P)(50) = 20 ?; A computer keeps its page tables in memory. The time required to read a word from the page table is 50ns. To reduce this overhead, the computer has a TLB, which holds 32 (virtual page, physical page frame) pairs and can ... : 10ns + (1 - p) 50ns = 20ns p =4/5 = .80 The TLB hit rate has to be 80% for a mean access time of 20ns.

Why the formula used here is not P(10) + (1-P)(50) = 20 ?;A computer keeps its page tables in memory. The time required to read a word from the pagetable is 50ns. To redu...

rahuljai

1.3k views

rahuljai asked Dec 3, 2018

0 votes

0 answers

9

made easy tt2
IS THE ANSWER 1.794??

IS THE ANSWER 1.794??

Gate Fever

581 views

Gate Fever asked Nov 3, 2018

2 votes

1 answer

10

My doubt on TLB and page fault
First read this whole thing what I am writing below: Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then, EMAT=p( T+M )+( 1-p ) (T+M+M) T=TLB access time, M= ... if there page fault occurs then how does the last calculated EMAT here affects the first Estimated memory access time which we have calculated using TLB?

First read this whole thing what I am writing below:Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then,EMAT=p( T+M...

Akash Kumar Roy

2.7k views

Akash Kumar Roy asked Apr 5, 2018

0 votes

1 answer

11

Hit Ratio and miss ratio question
In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit and miss. Is there any patterns for this or could be explained.

In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit a...

nirupama thakur

2.0k views

nirupama thakur asked Mar 17, 2018

1 votes

1 answer

12

CO Page fault
How this is 20000? the array is in RMO and we are accessing like CMO then for each entry there should be PF.

How this is 20000? the array is in RMO and we are accessing like CMO then for each entry there should be PF.

Ashwin Kulkarni

600 views

Ashwin Kulkarni asked Jan 19, 2018

1 votes

1 answer

13

ace test series

rohit vishkarma

472 views

rohit vishkarma asked Jan 2, 2018

2 votes

0 answers

14

ETA-TLB-page fault
TLB lookup time = 20 ns TLB hit ratio = 99% Memory access time = 100 ns Page fault rate = 0.05% Swap time = 5000000 ns What is the EAT if we assume that all pages currently in main memory are dirty?

TLB lookup time = 20 nsTLB hit ratio = 99%Memory access time = 100 nsPage fault rate = 0.05%Swap time = 5000000 nsWhat is the EAT if we assume that all pages currently in...

Tuhin Dutta

550 views

Tuhin Dutta asked Dec 20, 2017

2 votes

2 answers

15

TLB HITS
What is the average memory access time (correct to two decimal places) when you have the following memory hierarchy? Assume that (i) the cache uses physical addresses, (ii) the CPU stalls until the data is delivered, (iii) everything fits into the memory, and (iv) the hardware does the page table walk and updates TLB.

What is the average memory access time (correct to two decimal places) when you have the following memory hierarchy? Assume that (i) the cache uses physical addresses, (i...

Parshu gate

689 views

Parshu gate asked Nov 11, 2017

4 votes

3 answers

16

cache hit ratio
Consider an array A[200] and each element occupies 8-words. A 64-word cache is used and divided into 16-word blocks. What is the hit ratio for the following code segment: for(int i=0; i<200; i++) A[i] = A[i]+5 0.85 0.65 0.95 0.75

Consider an array A[200] and each element occupies 8-words. A 64-word cache is used and divided into 16-word blocks. What is the hit ratio for the following code segment:...

Parshu gate

1.3k views

Parshu gate asked Nov 10, 2017

3 votes

2 answers

17

Performance c
Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2 cache and main memory with 100% of the hit rate and 200 cycles when hit in main memory to access ... by 15% then the improvement in L1 miss time is ____________(upto 2 decimals) 1. 2.14 2. 2.78 3. 1.48 4. 1.14

Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2...

akb1115

1.1k views

akb1115 asked Oct 15, 2017

5 votes

1 answer

18

Multilevel TLB performance
A computer has a 128-entry $L_1$ TLB, 1024-entry $L_2$ TLB, and uses page size of 4KB. A program reads a 1MB array, one byte at a time from start to end, 10 times. Assuming the TLBs are directly mapped and initially empty, and no other memory is accessed, find TLB hits and misses of both $L_1$ and $L_2$ TLB (array is page aligned).

A computer has a 128-entry $L_1$ TLB, 1024-entry $L_2$ TLB, and uses page size of 4KB. A program reads a 1MB array, one byte at a time from start to end, 10 times. Assumi...

habedo007

984 views

habedo007 asked Aug 8, 2017

1 votes

1 answer

19

Average access time
Consider two level memory systems in which the average access time is 150 ns without level L1 . The level 1 access time is 20 ns . The average access time with L1 is 40 ns. The hit ration of L1 in percengage........ Plz help me to find the correct answer.. I got 88%

Consider two level memory systems in which the average access time is 150 ns without level L1 . The level 1 access time is 20 ns . The average access time with L1 is 40 n...

mystylecse

2.8k views

mystylecse asked Aug 6, 2017

1 votes

0 answers

20

tlb segmentation paging
Consider a memory system consists of a single external cache with an access time of 30ns and a hit rate of 0.85, and a main memory with an access time of 80ns. Now we add virtual memory to the system. The TLB is implemented internal to the processor chip and takes ... memory access time of the system with virtual memory?( Marks: 0.00 ) 8ns 30ns 40ns 51ns

Consider a memory system consists of a single external cache with an access time of 30ns and a hit rate of 0.85, and a main memory with an access time of 80ns. Now we add...

Neal Caffery

917 views

Neal Caffery asked Jan 17, 2017

1 votes

3 answers

21

TLB paging
Consider a system with 2-levels of paging and a TLB with hit rate of 95% and TLB access time of 1ns. Find the effective memory access time if there’s a data cache whose hit rate is 85% and cache access time is 1ns, and main memory access time is 100ns. 100ns. 27ns 25ns 30ns 20ns

Consider a system with 2-levels of paging and a TLB with hit rate of 95% and TLB access time of 1ns. Find the effective memory access time if there’s a data cache whose...

Neal Caffery

3.7k views

Neal Caffery asked Jan 17, 2017

0 votes

2 answers

22

In a two level hierarchy if the top level has an access time of 8ns and the bottom level has an access time of 60 ns.

In a two level hierarchy if the top level has an access time of 8ns and the bottom level has an access time of 60 ns. What is the hit ratio in top level required to give ...

rahuldb

3.0k views

rahuldb asked Nov 10, 2016

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true