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Recent questions tagged hit-ratio

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A demand paging uses a TLB and a single level page table stored in main memory. The memory access time is 5s. The page fault service time is 25s. If 70% of access is in TLB and of the remaining, 20% is not present in the main memory. The effective memory access time is? Thanks!
asked Jan 27, 2019 in Operating System Abhipsa 508 views
2 votes
1 answer
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Consider a system where TLB lookup time is $25$ ns and memory access time is $200$ ns, respectively. Assuming a virtual address space of $2$ KB, page size of $32$ bytes, and a PTE size of $2$ bytes, what is the minimum TLB hit ratio that results in an average v2p (virtual to physical) translation latency of $185$ ns?
asked Jan 13, 2019 in Operating System dd 229 views
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1 answer
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Why the formula used here is not P(10) + (1-P)(50) = 20 ?; A computer keeps its page tables in memory. The time required to read a word from the page table is 50ns. To reduce this overhead, the computer has a TLB, which holds 32 (virtual page, physical page frame) pairs and can do ... Solution: 10ns + (1 - p) 50ns = 20ns p =4/5 = .80 The TLB hit rate has to be 80% for a mean access time of 20ns.
asked Dec 3, 2018 in Operating System rahuljai 605 views
2 votes
1 answer
4
First read this whole thing what I am writing below: Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then, EMAT=p( T+M )+( 1-p ) (T+M+M) T=TLB access time, M=memory access time( ... TLB and if there page fault occurs then how does the last calculated EMAT here affects the first Estimated memory access time which we have calculated using TLB?
asked Apr 5, 2018 in Operating System Akash Kumar Roy 1.1k views
0 votes
1 answer
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In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit and miss. Is there any patterns for this or could be explained.
asked Mar 17, 2018 in CO and Architecture nirupama thakur 738 views
1 vote
1 answer
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How this is 20000? the array is in RMO and we are accessing like CMO then for each entry there should be PF.
asked Jan 19, 2018 in CO and Architecture Ashwin Kulkarni 157 views
1 vote
1 answer
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2 votes
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TLB lookup time = 20 ns TLB hit ratio = 99% Memory access time = 100 ns Page fault rate = 0.05% Swap time = 5000000 ns What is the EAT if we assume that all pages currently in main memory are dirty?
asked Dec 20, 2017 in Operating System Tuhin Dutta 262 views
2 votes
2 answers
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What is the average memory access time (correct to two decimal places) when you have the following memory hierarchy? Assume that (i) the cache uses physical addresses, (ii) the CPU stalls until the data is delivered, (iii) everything fits into the memory, and (iv) the hardware does the page table walk and updates TLB.
asked Nov 12, 2017 in Databases Parshu gate 371 views
4 votes
4 answers
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Consider an array A[200] and each element occupies 8-words. A 64-word cache is used and divided into 16-word blocks. What is the hit ratio for the following code segment: for(int i=0; i<200; i++) A[i] = A[i]+5 0.85 0.65 0.95 0.75
asked Nov 10, 2017 in CO and Architecture Parshu gate 601 views
3 votes
2 answers
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Consider the system have L1 data cache with 50 percent of hit rate and take 2 cycles when hit in L1 cache, L2 cache with 70% of hit rate and take 15 cycles when hit in L2 cache and main memory with 100% of the hit rate and 200 cycles when hit in main memory to access a block. ... improved by 15% then the improvement in L1 miss time is ____________(upto 2 decimals) 1. 2.14 2. 2.78 3. 1.48 4. 1.14
asked Oct 15, 2017 in CO and Architecture akb1115 470 views
3 votes
1 answer
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A computer has a 128-entry $L_1$ TLB, 1024-entry $L_2$ TLB, and uses page size of 4KB. A program reads a 1MB array, one byte at a time from start to end, 10 times. Assuming the TLBs are directly mapped and initially empty, and no other memory is accessed, find TLB hits and misses of both $L_1$ and $L_2$ TLB (array is page aligned).
asked Aug 8, 2017 in Operating System habedo007 510 views
1 vote
1 answer
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Consider two level memory systems in which the average access time is 150 ns without level L1 . The level 1 access time is 20 ns . The average access time with L1 is 40 ns. The hit ration of L1 in percengage........ Plz help me to find the correct answer.. I got 88%
asked Aug 6, 2017 in CO and Architecture mystylecse 1.5k views
1 vote
0 answers
14
Consider a memory system consists of a single external cache with an access time of 30ns and a hit rate of 0.85, and a main memory with an access time of 80ns. Now we add virtual memory to the system. The TLB is implemented internal to the processor chip and takes 4ns to do a ... the effective memory access time of the system with virtual memory?( Marks: 0.00 ) 8ns 30ns 40ns 51ns
asked Jan 17, 2017 in Operating System Neal Caffery 524 views
1 vote
3 answers
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Consider a system with 2-levels of paging and a TLB with hit rate of 95% and TLB access time of 1ns. Find the effective memory access time if there’s a data cache whose hit rate is 85% and cache access time is 1ns, and main memory access time is 100ns. 100ns. 27ns ​​​​​​​ 25ns ​​​​​​​ 30ns ​​​​​​​ 20ns
asked Jan 17, 2017 in Operating System Neal Caffery 1.6k views
2 votes
3 answers
16
Consider a paging system uses, TLB’s access time is 30 ns and memory access time is 200ns. If the effective memory access time is 150ns, what will be the hit ratio of TLB?
asked Nov 8, 2016 in Operating System Veerendra V 3.6k views
1 vote
1 answer
17
The hit ratio of a Transaction Look Aside Buffer (TLAB) is 80%. It takes 20 nanoseconds (ns) to search TLAB and 100 ns to access main memory. The effective memory access time is _____ 36 ns 140 ns 122 ns 40 ns
asked Jul 21, 2016 in Operating System jothee 3.2k views
5 votes
1 answer
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Consider an array has 100 elements and each element occupies 4 words .A 32 bit word cache is used and divided into a block of 8 words .What is the hit rate of this for(i=0; i<10; i++) for(j=0; j<10; j++); A[i][j] = A[i][j]+10; Column major is used here. How to improve Hit rate ?
asked Jul 21, 2016 in CO and Architecture shekhar chauhan 1.2k views
8 votes
4 answers
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Consider an array A[100] and each element occupies 4 word. A 32 word cache is used and divided into 8 word blocks. What is the hit ratio for the following statement. for(i=0;i<100;i++) A[i]=A[i]+10 What mapping is going to be used in the Solution ?
asked Jul 20, 2016 in CO and Architecture shekhar chauhan 2.4k views
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