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Consider a 5 stage pipeline that allows overlapping of all instructions except branch instructions. The target of branch instructions is not available until the branch instruction is completed. Let each stage delay is 20 ns and there are 30% branch instructions.
What is the performance gain of pipeline over non-pipeline

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CPI=1+0.3*4(stall due to branch instruction)=1.12

instruction execution time in non pipeline processor=20*3=100ns

instruction execution time in non pipeline processor=1.12*20=22.4ns;

speedup=100/22.4=4.46
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