Recent questions tagged pipelining / GATE Overflow for GATE CSE

3 votes

1 answer

271

CO-Pipelining
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ... I91. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction ...

AnilGoudar

899 views

AnilGoudar asked Jan 16, 2018

1 votes

2 answers

272

Co & Arch

gauravkc

468 views

gauravkc asked Jan 15, 2018

3 votes

1 answer

273

MadeEasy Test Series 2018: CO & Architecture - Pipelining
for Instructions results in both control and data dependency, what will be the penalty 3 or 5, please explain.

for Instructions results in both control and data dependency, what will be the penalty 3 or 5, please explain.

charul

268 views

charul asked Jan 15, 2018

3 votes

1 answer

274

pipelining
is it 1.92 or 1.94 i want conformation...

is it 1.92 or 1.94 i want conformation...

pranab ray

433 views

pranab ray asked Jan 15, 2018

3 votes

0 answers

275

#Data Hazards #Operand Forwarding #CO
Is there any difference in calculating data hazards and dependencies? Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS TRUE. Doubt 2:Calculation of RAW,WAR,WAW hazards include ... adjacent.IS THIS TRUE There are many sources which are confusing Please Explain how to calculate dependencies and hazards.

Is there any difference in calculating data hazards and dependencies?Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS ...

rasto mapp

602 views

rasto mapp asked Jan 13, 2018

3 votes

0 answers

276

Speedup In pipelining
Actually, In this problem what will, we consider getting the answer(upper bound or lower bound) and why?

Actually, In this problem what will, we consider getting the answer(upper bound or lower bound) and why?

thepeeyoosh

714 views

thepeeyoosh asked Jan 13, 2018

1 votes

1 answer

277

pipielining
In questions where we are asked to find number of cycles taken for a set of instructions, if an IF overlaps with MEM (which generally is a structural hazard) we still let it overlap in the solution. So does IF and MEM execute in split phase? If so I have read ... (a comment by someone) that it takes one whole cycle for MEM to function and cannot be in a split phase? Please help me out.

In questions where we are asked to find number of cycles taken for a set of instructions, if an IF overlaps with MEM (which generally is a structural hazard) we still let...

Warlock lord

281 views

Warlock lord asked Jan 12, 2018

3 votes

2 answers

278

Pipeline Efficiency
The speed up of a pipelined processor is $5.4,$ operating at $2$ GHZ frequency with efficiency $82\%$. What will be no. of stages available in this processor$?$

The speed up of a pipelined processor is $5.4,$ operating at $2$ GHZ frequency with efficiency $82\%$.What will be no. of stages available in this processor$?$

saxena0612

795 views

saxena0612 asked Jan 10, 2018

2 votes

0 answers

279

Ace Test series: CO & Architecture - Pipelining
Consider the following program which is executed on $4$ stage pipelined processor. IF=$2$ clocks/word ID=$2$ clocks/word EX stage takes $2$ clocks for register operands and $3$ clocks for memory operand WR stage takes ... Minimum number of clocks needed to complete the above program is _________________ Note:Pipeline stage sequence is IF,ID,EX and WR

Consider the following program which is executed on $4$ stage pipelined processor.IF=$2$ clocks/wordID=$2$ clocks/wordEX stage takes $2$ clocks for register operands and ...

rasto mapp

1.4k views

rasto mapp asked Jan 10, 2018

3 votes

2 answers

280

pipelining
We have two designs P 1 and P 2 for a synchronous pipeline processor. P1 has 8 pipeline stages with execution time of 3 nsec, 2 nsec, 4 nsec, 7 nsec, 2 nsec, 5 nsec, 4 nsec and 2 nsec while design P2 has 5 stages each with 6 nsec execution time. How much time can be saved using design P2 over design P1 for executing 400 instructions?

We have two designs P 1 and P 2 for a synchronous pipeline processor. P1 has 8 pipeline stages with execution time of 3 nsec, 2 nsec, 4 nsec, 7 nsec, 2 nsec, 5 nsec, 4 ns...

Parshu gate

1.1k views

Parshu gate asked Jan 2, 2018

2 votes

1 answer

281

pipelining
Assume branch instructions occur 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% of the time with ... instructions are loads and 30% of these introduce load delay hazards. What is the New CPI due to load delay slots and branch hazards?

Assume branch instructions occur 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forward...

Parshu gate

388 views

Parshu gate asked Jan 1, 2018

3 votes

2 answers

282

MadeEasy Test Series: CO & Architecture - Speedup

Kalpataru Bose

922 views

Kalpataru Bose asked Dec 31, 2017

2 votes

1 answer

283

COA-PIPELINE
An instruction pipeline consists of following 5 stages: IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = Register Write Back Now consider the following code: Assume that each stage takes 1 clock cycle for ... are required to execute the code, without operand forwarding over a bypass network ________. Someone please confirm this i am getting 12

An instruction pipeline consists of following 5 stages: IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Me...

junaid ahmad

954 views

junaid ahmad asked Dec 27, 2017

0 votes

2 answers

284

Test series
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ns, 10 ns, 8 ns ... of this program, the time (in ns) needed to complete the program is ________ . (A) 612 (B) 1854 (C) 1133 (D) 578

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction ...

Chirag arora

748 views

Chirag arora asked Dec 25, 2017

0 votes

0 answers

285

#Instruction-pipeline Data hazard between two consecutive memory access instruction
Although the following instructions do not make much sense but if such case occurs, is data forwarding from MA of I1 to MA of I2 allowed? Or will it result in some stall? Please add some reference, I couldn't find any yet. I1: Load A //A<-Mem[address] I2: Store Adress2, A // Mem[Address2] <- A

Although the following instructions do not make much sense but if such case occurs, is data forwarding from MA of I1 to MA of I2 allowed? Or will it result in some stall?...

AskHerOut

473 views

AskHerOut asked Dec 22, 2017

3 votes

0 answers

286

Hamacher
7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possibility, the processor has a four stage pipeline and one delay slot, and in second possibility, ... the single delay slot. For the second alternative, the compiler is able to fill the second slot 25 percent of the time.

7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possi...

Tesla!

1.4k views

Tesla! asked Dec 19, 2017

1 votes

1 answer

287

Pipeline
We have 10 stage pipeline , where the branch target conditions are resolved at stage 5 . How many stalls are there for an incorrectly predicted branch ? Plz draw a diagram.

We have 10 stage pipeline , where the branch target conditions are resolved at stage 5 . How many stalls are there for an incorrectly predicted branch ?Plz draw a diagram...

dragonball

2.3k views

dragonball asked Dec 17, 2017

1 votes

1 answer

288

Doubt in Pipelining Terminology
In pipelining questions we have "If operand forwarding is there " and "If operand forwarding is not there " Please explain this difference and how to draw the chart for both the cases .

In pipelining questions we have "If operand forwarding is there " and "If operand forwarding is not there " Please explain this difference and how to draw the chart f...

Parshu gate

389 views

Parshu gate asked Dec 10, 2017

0 votes

0 answers

289

Pipeline
Consider two pipeline designs O: having max ( all stage delay ) = 800 ns. N: having max ( all stage delay ) = 600 ns. Find the #instructions in the pipeline design O?

Consider two pipeline designsO: having max ( all stage delay ) = 800 ns.N: having max ( all stage delay ) = 600 ns.Find the #instructions in the pipeline design O?

Tuhin Dutta

406 views

Tuhin Dutta asked Dec 3, 2017

0 votes

1 answer

290

When to assume Structural hazards exists if not mentioned in instruction pipeline-self doubt
When shall we assume structural hazard?Like if nothing is mentioned if data and instruction are fetched via single port,can we assume 'MA' (memory access stage) and 'IF' (instruction ... it always the case if nothing is told? https://gateoverflow.in/102565/operand-forwarding-in-pipeline

When shall we assume structural hazard?Like if nothing is mentioned if data and instruction are fetched via single port,can we assume 'MA' (memory access stage) and 'IF' ...

Surajit

319 views

Surajit asked Dec 1, 2017

2 votes

1 answer

291

Pipelining

Parshu gate

572 views

Parshu gate asked Nov 29, 2017

0 votes

2 answers

292

Definition of Ideal Pipeline
What is the definition of an ideal pipeline? On searching over the internet I found only speed up formulas but no where the difference between ideal and non-ideal was mentioned.

What is the definition of an ideal pipeline?On searching over the internet I found only speed up formulas but no where the difference between ideal and non-ideal was ment...

Sourajit25

2.1k views

Sourajit25 asked Nov 26, 2017

1 votes

0 answers

293

[Self Doubt] previous year explanation
https://gateoverflow.in/683/gate2000-12 Can you please explain the meaning of the highlighted portion of the text. This is an explanation by Arjun Sir

https://gateoverflow.in/683/gate2000-12Can you please explain the meaning of the highlighted portion of the text. This is an explanation by Arjun Sir

Anshul Shankar

224 views

Anshul Shankar asked Nov 23, 2017

3 votes

1 answer

294

Hamacher Instruction Pipelining Doubt
Can anyone explain the concept of branch folding, I didn't get it after reading from hamacher.Further it was explained using this diagram,I have a doubt here : Is it possible to have two decode operations in the same cycle (Cycle 6 D3 and D5) will it not be a structural hazard as both the instructions are using the same device?

Can anyone explain the concept of branch folding, I didn't get it after reading from hamacher.Further it was explained using this diagram,I have a doubt here : Is it poss...

Sourajit25

1.2k views

Sourajit25 asked Nov 22, 2017

3 votes

0 answers

295

[Self Doubt] [Previous Years] When to take buffers or not in a pipeline??
https://gateoverflow.in/3690/gate2004-it-47 https://gateoverflow.in/1314/gate2009-28 Going through both the question I am a bit Confused with the logic of when to take the buffers in pipeline or not..

https://gateoverflow.in/3690/gate2004-it-47https://gateoverflow.in/1314/gate2009-28Going through both the question I am a bit Confused with the logic of when to take the...

Anshul Shankar

446 views

Anshul Shankar asked Nov 21, 2017

0 votes

1 answer

296

Self Doubt
Given question is: Consider the following program segment used to execute on a risc pipleline where all the stages are taking 1 cycle to complete the operation except MA stage (4th stage ). MA stage takes two cycle to complete opeartion. How many cycles are are required ... doubt is in the pipelining diagram why we are not decoding i3 when stalls are there for i2 in clock cycle 4 and 5

Given question is: Consider the following program segment used to execute on a risc pipleline where all the stages are taking 1 cycle to complete the operation except MA...

Anshul Shankar

568 views

Anshul Shankar asked Nov 20, 2017

2 votes

1 answer

297

Pipelining Problem
How to slove this type of problems? How to understand the problem?Please help me out. Given answer is 31

How to slove this type of problems? How to understand the problem?Please help me out. Given answer is 31

Parshu gate

1.4k views

Parshu gate asked Nov 18, 2017

1 votes

0 answers

298

What does CPI in Pipelining actually mean?
Require detailed explanation along with formulas and which formula to use depending upon each scenario

Require detailed explanation along with formulas and which formula to use depending upon each scenario

Namit Dhupar

4.1k views

Namit Dhupar asked Nov 16, 2017

1 votes

1 answer

299

Pipeline performance / cost ratio.
The time taken to execute a program on a non-pipelined machine is t. The same program is then executed on an m stage pipeline. The cost of all the logic stages of the pipeline is given by c and h is the cost of each latch. The delay incurred by each pipeline stage is d. What is ... 2. (mc + m2h)/(t + md) 3. m/(ct + mht + m2cd + m3dh) 4. m/(ct + ht + mcd + m2dh)

The time taken to execute a program on a non-pipelined machine is t. The same program is then executed on an m stage pipeline. The cost of all the logic stages of the pip...

Hemant Parihar

1.3k views

Hemant Parihar asked Nov 15, 2017

1 votes

4 answers

300

Pipe-lining with floating point operation..!!
Suppose that a task makes extensive use of floating point operations with 40% of the time is consumed by floating point operations. With a new hardware design, the floating point module is speeded up by a factor of 4. What is the overall speedup? A. 1.05 B. 1.42 C. 2.5 D. 4 Please explain the little bit problem also.

Suppose that a task makes extensive use of floating point operations with 40% of the time is consumed by floating point operations. With a new hardware design, the floati...

Hemant Parihar

4.0k views

Hemant Parihar asked Nov 15, 2017

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