Register
Pipelining Explained

Recent questions tagged pipelining

3 3 votes
2 2 answers
1.4k
1.4k views
Gateforum Test Series: CO & Architecture - Pipelining
User Avatar
0 0 votes
0 0 answers
1.6k
1.6k views
pipeline
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and bra...
User Avatar
0 0 votes
1 1 answer
1.2k
1.2k views
adressing modes
For Given machine instructionsLW R4 #400L1:LW R1, 0,(R4)LW R2 400(R4)ADDI R3, R1, R2SW R3, 0(R4)SUB R4, R4, #4BNZ R4, L1on a 5 stage pipeline processor, 1 clock cycle per...
User Avatar
2 2 votes
2 2 answers
3.5k
3.5k views
Pipelining
User Avatar
0 0 votes
0 0 answers
2.0k
2.0k views
made easy co tt1
I THINK ANSWER SHOULD BE 462,THEY HAVE GIVEN ANSWER 554, WHICH I FEEL IS WRONG!
User Avatar
0 0 votes
0 0 answers
1.0k
1.0k views
Self Doubt
In this question, https://gateoverflow.in/69709/pipelining Kapil Sir had commented that we can do split phase access between memory access(MA) stage and execute(EX) stag...
User Avatar
0 0 votes
0 0 answers
513
513 views
SELF DOUBT
PLEASE explain what is operand forwarding and how we are going to implement this in stages during execution of the instruction ???and also when to use it in according to...
User Avatar
0 0 votes
0 0 answers
749
749 views
test series
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, O...
User Avatar
0 0 votes
0 0 answers
1.6k
1.6k views
SELF DOUBT
S1S2S3S4I1:1212I2:2121I3:1121I4:2121 Consider a pipeline processor with 4 stages S1 to S4. We want to execute the following loopfor (i = 1; i < = 10; i++) {I1, I2, I3, I4...
User Avatar
3 3 votes
2 2 answers
629
629 views
Gateforum Test Series: CO & Architecture - Pipelining
User Avatar
2 2 votes
1 1 answer
648
648 views
Gateforum Test Series: CO & Architecture - Pipelining
User Avatar
0 0 votes
1 1 answer
1.2k
1.2k views
made easy test series
ans given is 1.92
User Avatar
0 0 votes
0 0 answers
432
432 views
Doubt clearing
Incase of operand forwarding in RISC pipeline with stages Instruction fetch (IF)Instruction decode (ID)Execute (EX)Memory Access (MA)Write Back (WB)If it is not mentioned...
User Avatar
0 0 votes
0 0 answers
479
479 views
CO & Architecture - Pipelining
Design a binary multiply pipeline unit for two 4 bit operands.Use minimum number of CSA's and CPA's.Show all interconnections and bus width in the schematic diagram.Calcu...
User Avatar
2 2 votes
1 1 answer
3.7k
3.7k views
Pipeline : Number of RAW dependencies
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding.I1: ADD R0,R1,R2 (R0=R1+R2)I2: SUB R3,R0,R2I3:MUL R4,R3,R0I4:D...
User Avatar
1 1 vote
1 1 answer
983
983 views
DOUBT: isn't this is a pipelining question
How to do these questions? there is no information about no. of stages an instruction takes? Consider the 2 GHz clock frequency processor used execute the following progr...
User Avatar
0 0 votes
1 1 answer
469
469 views
Test_CO1_Q35
Assume branch instruction occurs 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forward...
User Avatar
1 1 vote
1 1 answer
2.1k
2.1k views
MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction outp...
User Avatar
0 0 votes
0 0 answers
1.1k
1.1k views
Pipelining
Approach :
User Avatar
0 0 votes
1 1 answer
588
588 views
Addressing modes + pipelining
I got Option D , and Are we saving 1 cycle by replacement ? ( if yes then may be solved it correct else i am wrong somewhere )
User Avatar
2 2 votes
0 0 answers
865
865 views
Is superscalar operations in pipelining part of gate syllabus
Is superscalar operations in pipelining part of gate syllabus?
User Avatar
0 0 votes
1 1 answer
1.5k
1.5k views
Branch prediction in pipelining part of syllabhs?
Is branch prediction in pipelining im Co and architecture part of gate syllabus?
User Avatar
1 1 vote
0 0 answers
613
613 views
Pipeline performance reduced if different stages have different execution delays
The pipeline performance is reduced if the different stages of a pipeline have different delaysI know that in the pipeline, Tclock is taken as the Max(Ti)+Tbuffer time, a...
User Avatar
3 3 votes
1 1 answer
2.8k
2.8k views
Minimum clock cycle
User Avatar
0 0 votes
0 0 answers
1.6k
1.6k views
#CO pipeline doubt
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of...
User Avatar
0 0 votes
1 1 answer
402
402 views
UNDEFINED
in a 5 stage pipeline processor a program consist of 50 instruction suppose there are 20% instruction require 1 extra stall cycle what is the cpi from this execution ?
User Avatar
0 0 votes
0 0 answers
409
409 views
#CO Gate 2009 Self Doubt.
Original question- https://gateoverflow.in/1314/gate2009-28In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stag...
User Avatar
0 0 votes
0 0 answers
601
601 views
Self Doubt : Pipe lining
Given 100 instructions executed on a 5 stage pipeline . probability (p) that an instruction is branch is p. Branch penalty 4.Assuming that each stage of pipeline takes 1 ...
User Avatar
0 0 votes
0 0 answers
1.8k
1.8k views
Operand Forwarding Doubt
I dont understand here:- Load R2,(R3)1. Fetch2. Decode: Rz < - Address of R3 given in instruction3. Compute : NOP4. Memory Memory address < -[RZ] , read memory, Ry < -Mem...
User Avatar
Page: