Operand Forwarding Doubt

Question

I dont understand here:- 

Load R2,(R3)

1. Fetch

2. Decode: Rz <--- Address of R3 given in instruction

3. Compute : NOP

4. Memory Memory address <---[RZ] , read memory, Ry <---MemData

5. R2 <--- [Ry]

 

If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??

Comments

Generally two caches are maintained one is I-cache where the instructions are stored and another is D-cache where the data are stored. This is done to avoid structural hazard because there might be two instructions one in fetch stage and other in memory stage but they cannot execute parallely if there is only one memory instance.

Maybe in this case in D-cache there is a miss for which the we have to access the MM(or higher level caches) which increases the cycles required.

And I am not a teacher _/\_ :P

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Brother in figure its written that data is found in the cache and it takes 1 clock cycle.

And sir are u trying to say that the instruction i am trying to access in fetch stage and in memory stage both are parallel ??? I didn't actually get what u r trying to say above. thats ok about structual hazard.

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No I didn't say that..

See suppose there are 10 instructions in a pipeline. Let Ix be in it's memory stage while Iy is in it's fetch stage.

We fetch instructions from memory right? And the memory data are obviously from memory. What I mean to say here is both the fetch and memory stages require to access the memory.

But then if this is the case then Ix and Iy cannot execute in memory and fetch stage(respectively) parallely. Iy has to wait creating a stall.

This can be called a structural hazard because due to the shortage of resources (1 cache) one of the instructions has to be delayed.

To prevent this we split the cache into two. One is I-cache for facilitating the fetching of instructions (so Iy can now fetch instructions from here) and another is D-cache which contains memory data(so that Ix can get it's memory operands at the same time).

Here in your case the I-cache contains instructions which take 1 clock cycle to access. But there is miss in D-cache for which we have to go to higher level caches or main memory ultimately taking 3cycles.

I hope this is clear now.

And Brother aur Sir ek saath!! :v