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Consider a non­pipelined processor design which has a cycle time of 10ns and average CPI of

1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is
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Initially it was taking cycle time of 10ns. (unpipe)

After pipelined, CT cycle time is max of all stage i.e., 2ns.

Speed up = 10/2 = 5
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here nothing is told about n, so in that case we'll take n = infinity.

when n = infinity,

$S$ = $\frac{T_{n}}{t_{p}}$

where $T_{n}$ is the time to execute a single instruction in Non-pipelined processor.

$t_{p}$ is the clock cycle time in pipelined processor.

So, $T_{n}$ = CPI * 10ns = 14ns

$t_{p}$ = 2 ns

S = 7
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Speed up = Exec. time non pipeline/ Exec. time pipeline

                =10*1.4/2 = 7

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