speedup in pipelining made easy & nptel

Question

Which approach is correct?

ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf

nptel assignment q-1

Caption

 

Comments

@farmanahmed888 Your answer is correct. Made easy has given incorrect ans, they forgot to add register delay.

Let total #instructions = x

In non-pipeline total time taken = (2+8+6+4+12)*x = 32*x ns

In pipeline cycle time taken = max(2,4,5,4,12) + 2ns = 14ns

Total #clock cycles to execute x instruction = (5+x-1) = 4+x

total time taken (in pipeline) = (4+x)*14 ≈ 14*x

Speedup = Non-pipeline time / Pipeline time = $\frac{32*x}{14*x} = 2.28$

Answer 1

yeah it is 2.66 only because in question the buffers are placed in between the statges,so the 12 ns stage has no buffer so the maximum latency is 12ns for pipeline.

Comments

ok

---

@Prabhas @chenna keshava Every stage should have an associated buffer right? The clock is connected to these buffers only and based on the Clock Cycle data is transmitted. So if last stage does not have a buffer how will the clock synchronize the data flow??

Answer 2

We don’t use reg delays in non-pipelined systems .
We use reg. delays in pipelined processors to prevent hazards , signaling other stages (which are also working simultaneously ) and for buffer storage , which is not needed in non-pipelined.

so total time for 1 task in non-pipelined system is = (2+6+8+4+12) = 32
so total time for 1 task in non-pipelined system is = 12 = max(2,6,8,4,12)+reg delay(0 or ignorable delay after max-time taking stage) .

performance gain = 32/12 =2.666