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Recent questions tagged memory-interfacing
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Made Easy Test Series 2024
A dynamic RAM has a refresh cycle of 32 times per msec. Each refresh operation requires $100$ nanosecond and a memory cycle requires $200$ nanosecond. What percentage of memory's total operating time is required for refreshes?
A dynamic RAM has a refresh cycle of 32 times per msec. Each refresh operation requires $100$ nanosecond and a memory cycle requires $200$ nanosecond. What percentage of ...
Ray Tomlinson
308
views
Ray Tomlinson
asked
Sep 6, 2023
CO and Architecture
co-and-architecture
made-easy-test-series
memory-interfacing
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11
votes
2
answers
2
GATE CSE 2023 | Question: 32
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip select $\text{(CS)}$ port of these memory blocks through a decoder as shown in the figure. The ... options is $\text{CORRECT}?$ $(0,1,2,3)$ $(0,1024,2048,3072)$ $(0,8,16,24)$ $(0,0,0,0)$
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected t...
admin
6.1k
views
admin
asked
Feb 15, 2023
CO and Architecture
gatecse-2023
co-and-architecture
memory-interfacing
2-marks
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0
votes
1
answer
3
The number of address lines required to address 8 GB memory is a) 8 b) 1024 c) 32 d) 33 . Please help
Jeetmoni saikia
863
views
Jeetmoni saikia
asked
Oct 11, 2022
CO and Architecture
co-and-architecture
digital-logic
memory-interfacing
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0
votes
1
answer
4
prepladder question bank
How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable.
How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable.
shreyo
485
views
shreyo
asked
Sep 12, 2022
CO and Architecture
co-and-architecture
memory-interfacing
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0
votes
1
answer
5
Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So: a) How many multiplexer is needed? b) What type of multiplexer is required i.e size of multiplexer? c) Describe decoder used to select address of memory unit
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So:a) How many multiplexer is needed?b) What type of multip...
kidussss
283
views
kidussss
asked
Sep 1, 2022
CO and Architecture
co-and-architecture
memory-interfacing
branch-conditional-instructions
reference-book
digital-logic
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1
votes
1
answer
6
NIELIT Scientific Assistant A 2020 November: 55
A $26-$bit address bus has maximum accessible memory capacity of ________ $\text{64 MB}$ $\text{16 MB}$ $\text{1 GB}$ $\text{4 GB}$
A $26-$bit address bus has maximum accessible memory capacity of ________$\text{64 MB}$$\text{16 MB}$$\text{1 GB}$$\text{4 GB}$
gatecse
573
views
gatecse
asked
Dec 9, 2020
CO and Architecture
nielit-sta-2020
co-and-architecture
memory-interfacing
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1
votes
2
answers
7
NIELIT 2016 DEC Scientist B (IT) - Section B: 37
How many address lines are needed to address each memory location in a $2048\times4$ memory chip? $10$ $11$ $8$ $12$
How many address lines are needed to address each memory location in a $2048\times4$ memory chip?$10$$11$$8$$12$
admin
852
views
admin
asked
Mar 31, 2020
CO and Architecture
nielit2016dec-scientistb-it
co-and-architecture
memory-interfacing
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0
votes
1
answer
8
NIELIT 2016 DEC Scientist B (CS) - Section B: 58
CPU consists of _______. ALU and Control Unit ALU, Control Unit and Monitor ALU, Control Unit and Hard disk ALU, Control Unit and Register
CPU consists of _______.ALU and Control UnitALU, Control Unit and MonitorALU, Control Unit and Hard diskALU, Control Unit and Register
admin
1.0k
views
admin
asked
Mar 31, 2020
CO and Architecture
nielit2016dec-scientistb-cs
co-and-architecture
memory-interfacing
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–
1
votes
4
answers
9
NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor? Static memory Dynamic memory ROM None of the option
Which memory is difficult to interface with processor?Static memoryDynamic memoryROMNone of the option
admin
1.4k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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–
1
votes
2
answers
10
NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time is Same as the access time. Longer than the access time. Shorter than the access time. Multiple of the access time.
For a memory system, the cycle time isSame as the access time.Longer than the access time.Shorter than the access time.Multiple of the access time.
admin
1.1k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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–
0
votes
1
answer
11
NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory has Lower bit density and higher power consumption Higher bit density and lower power consumption Lower bit density and lower power consumption None of the option
In comparison with static RAM memory, the dynamic RAM memory hasLower bit density and higher power consumptionHigher bit density and lower power consumptionLower bit dens...
admin
859
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
+
–
1
votes
1
answer
12
NIELIT 2017 July Scientist B (CS) - Section B: 30
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\times 4$ bits? $13$ $14$ $16$ $17$
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\...
admin
705
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
+
–
1
votes
3
answers
13
NIELIT 2017 DEC Scientist B - Section B: 28
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________ $2^{12}$ $2^{10}$ $2^{19}$ $2^{13}$
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________$2^{12}$$2^{10}$$2^{19}$$2^{13}$
admin
1.9k
views
admin
asked
Mar 30, 2020
CO and Architecture
nielit2017dec-scientistb
co-and-architecture
memory-interfacing
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–
0
votes
0
answers
14
No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each.No of chips required to design the memor...
Tuhin Dutta
2.4k
views
Tuhin Dutta
asked
May 7, 2019
CO and Architecture
co-and-architecture
memory-interfacing
+
–
1
votes
1
answer
15
ACE(COMPUTER ORGANIZATION)
Q.1 A 32 bit wide main memory unit with a capacity of 4GB is built using 128M *8 bit DRAM .the number of rows of memory cells in the DRAM chip is $2^{12}$ and time require to refresh operation is 20 nsec.total amount of time require to refresh the 4GB DRAM is………..? Ans-81.92 microsec. explanation ????
Q.1 A 32 bit wide main memory unit with a capacity of 4GB is built using 128M *8 bit DRAM .the number of rows of memory cells in the DRAM chip is $2^{12}$ and time requir...
BASANT KUMAR
438
views
BASANT KUMAR
asked
Jan 29, 2019
CO and Architecture
co-and-architecture
memory-interfacing
numerical-answers
+
–
0
votes
1
answer
16
MadeEasy Test Series: CO & Architecture - Memory Interfacing
Consider a DRAM that must be given a refresh cycle $64$ times per msec. Each refresh operation requires $100 \ nsec$ and a memory cycle requires $200 \ nsec$. The percentage of the memory’s total operating time must be given to refresh is _______ (upto $2$ decimal places)
Consider a DRAM that must be given a refresh cycle $64$ times per msec. Each refresh operation requires $100 \ nsec$ and a memory cycle requires $200 \ nsec$. The percent...
zeeshanmohnavi
466
views
zeeshanmohnavi
asked
Dec 26, 2018
CO and Architecture
co-and-architecture
made-easy-test-series
memory-interfacing
+
–
0
votes
0
answers
17
Hamacher
aditi19
306
views
aditi19
asked
Dec 8, 2018
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
memory-interfacing
effective-memory-access
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–
0
votes
0
answers
18
Self doubt on Memory Interfacing 2
A computer uses RAM Chips of 512X8 and ROM Chips of 2048x8. The computer needs 2K Bytes of RAM, 4K Bytes of ROM, and 4 interface units each with 4 registers. A Memory Mapped I/O configuration is used. How many RAM Chips and ROM Chips are required?
A computer uses RAM Chips of 512X8 and ROM Chips of 2048x8. The computer needs 2K Bytes of RAM, 4K Bytes of ROM, and 4 interface units each with 4 registers. A Memory Map...
Balaji Jegan
362
views
Balaji Jegan
asked
Nov 27, 2018
CO and Architecture
co-and-architecture
memory-interfacing
self-doubt
numerical-answers
+
–
0
votes
1
answer
19
Self doubt on Memory Interfaacing
A computer uses RAM Chips of 512X8 and ROM Chips of 2048x8. The computer needs 2K Bytes of RAM, 4K Bytes of ROM and 4 interface units each with 4 registers. An I/O mapped I/O configuration is used. How many RAM Chips and ROM Chips are required?
A computer uses RAM Chips of 512X8 and ROM Chips of 2048x8. The computer needs 2K Bytes of RAM, 4K Bytes of ROM and 4 interface units each with 4 registers. An I/O mapped...
Balaji Jegan
2.0k
views
Balaji Jegan
asked
Nov 26, 2018
CO and Architecture
co-and-architecture
memory-interfacing
self-doubt
numerical-answers
+
–
0
votes
1
answer
20
Mca / Bca term end examination IGNOU June 2018
How many chips of 512K * 8 are required for constructing 4M * 32 memory?
How many chips of 512K * 8 are required for constructing 4M * 32 memory?
Chandan567
500
views
Chandan567
asked
Nov 15, 2018
CO and Architecture
co-and-architecture
memory-interfacing
numerical-answers
mca-bca-ignou2018-exam
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