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Recent questions tagged memory-interfacing
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1 vote
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0 answers
382
382 views
how many 128*8 Ram chips are needed to provide a memory capacity of 2048 bytes?
how many 128*8 Ram chips are needed to provide a memory capacity of 2048 bytes?
Narasareddy_vajrala
382
views
asked
Oct 22, 2024
CO & Architecture
co-and-architecture
memory-interfacing
numerical-answers
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0 votes
2
answers
2 answers
783
783 views
Made Easy Test Series 2024
A dynamic RAM has a refresh cycle of 32 times per msec. Each refresh operation requires $100$ nanosecond and a memory cycle requires $200$ nanosecond. What percentage of ...
aashish1406
783
views
asked
Sep 6, 2023
CO & Architecture
co-and-architecture
made-easy-test-series
memory-interfacing
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48
48 votes
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5 answers
17.1k
17.1k views
GATE CSE 2023 | Question: 32
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected t...
admin
17.1k
views
asked
Feb 15, 2023
CO & Architecture
gatecse-2023
co-and-architecture
memory-interfacing
two-marks
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0
0 votes
1
1 answer
1.8k
1.8k views
The number of address lines required to address 8 GB memory is a) 8 b) 1024 c) 32 d) 33 . Please help
Jeetmoni saikia
1.8k
views
asked
Oct 11, 2022
CO & Architecture
co-and-architecture
digital-logic
memory-interfacing
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0
0 votes
1
1 answer
1.2k
1.2k views
prepladder question bank
How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable.
shreyo
1.2k
views
asked
Sep 12, 2022
CO & Architecture
co-and-architecture
memory-interfacing
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1
1 vote
1
1 answer
572
572 views
Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So:a) How many multiplexer is needed?b) What type of multip...
kidussss
572
views
asked
Sep 1, 2022
CO & Architecture
co-and-architecture
memory-interfacing
branch-conditional-instructions
reference-book
digital-logic
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1
1 vote
1
1 answer
943
943 views
NIELIT Scientific Assistant A 2020 November: 55
A $26-$bit address bus has maximum accessible memory capacity of ________$\text{64 MB}$$\text{16 MB}$$\text{1 GB}$$\text{4 GB}$
gatecse
943
views
asked
Dec 9, 2020
CO & Architecture
nielit-sta-2020
co-and-architecture
memory-interfacing
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1
1 vote
2
2 answers
1.4k
1.4k views
NIELIT 2016 DEC Scientist B (IT) - Section B: 37
How many address lines are needed to address each memory location in a $2048\times4$ memory chip?$10$$11$$8$$12$
admin
1.4k
views
asked
Mar 31, 2020
CO & Architecture
nielit2016dec-scientistb-it
co-and-architecture
memory-interfacing
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0
0 votes
1
answers
1 answer
1.5k
1.5k views
NIELIT 2016 DEC Scientist B (CS) - Section B: 58
CPU consists of _______.ALU and Control UnitALU, Control Unit and MonitorALU, Control Unit and Hard diskALU, Control Unit and Register
admin
1.5k
views
asked
Mar 31, 2020
CO & Architecture
nielit2016dec-scientistb-cs
co-and-architecture
memory-interfacing
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1
1 vote
4
4 answers
2.2k
2.2k views
NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor?Static memoryDynamic memoryROMNone of the option
admin
2.2k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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1
1 vote
2
2 answers
1.6k
1.6k views
NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time isSame as the access time.Longer than the access time.Shorter than the access time.Multiple of the access time.
admin
1.6k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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0
0 votes
1
1 answer
1.6k
1.6k views
NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory hasLower bit density and higher power consumptionHigher bit density and lower power consumptionLower bit dens...
admin
1.6k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017july-scientistb-cs
co-and-architecture
memory-interfacing
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