Recent questions tagged memory-interfacing

If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\...

A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________$2^{12}$$2^{10}$$2^{19}$$2^{13}$

Q.1 A 32 bit wide main memory unit with a capacity of 4GB is built using 128M *8 bit DRAM .the number of rows of memory cells in the DRAM chip is $2^{12}$ and time requir...

Consider a DRAM that must be given a refresh cycle $64$ times per msec. Each refresh operation requires $100 \ nsec$ and a memory cycle requires $200 \ nsec$. The percent...

How many chips of 512K * 8 are required for constructing 4M * 32 memory?

How many address and data lines in 1M×16 ROM system

How many 512×8 RAM chips are needed to provide a memory capacity of 2048 bytes

I know that correct answer is none of these But I need explanation with answer

Cache size 32 KBBlock size = 32 BytesAddress size = 28 bit.Associativity of Cache = 16Determine what is the hardware requirement to design the 16-way set associative cach...

Hi All,I have one doubt regarding avg access time in various levels of memory. There are 2 ways in which the processor is connected to various levels of memory.2 levelsCa...

A disk has 24 recording surfaces ,it has a total of 14,000 cylinders.there is an average of 400 sectors per track.Each sector contain 512 bytes of data a) using a 32 bit ...

In 16 bit processor like 8086, we have the concept of big Endian and small Endian which is related to even and odd bank of memory used in memory address interpretation.Fo...

1.6 Suppose that execution time for a program is directly proportional to instruction access time and that access to an instruction in the cache is 20 times faster than a...