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ISRO ECE 2013 | Digital Logic
 What is the division factor of the given clock divider circuit?$2$$3$$1.5$$2.5$
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ISRO ECE 2013 | Computer architecture
A memory system of size $16 \;\text{K}$ bytes is required to be designed using memory chips which have $12$ address lines and $4$ data lines each. The number of such chip...
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ISRO ECE 2013 | Digital Logic
If a counter having $10$ flip flops is initially at $0,$ what count will it hold after $2060$ pulses?$000\; 000\; 1100$$000 \;001\; 1100$$000 \;001\; 1000$$000 \;000\; 11...
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ISRO ECE 2013 | 2s compliment number
The two numbers represented in signed $\text{2s}$ complement form are $\text{P}= 11101101$ and $\text{Q}= 11100110.$ If $\text{Q}$ is subtracted from $\text{P},$ the valu...
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ISRO ECE 2013 |: Digital Logic
Which of the following is the Boolean function for majority voting, assuming $\text{A, B, C}$ are inputs and $\text{Y}$ is output?$\text{Y = AB + AC + BC}$$\text{Y = A + ...
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ISRO ECE 2013 | Digital Logic
What is the frequency and duty cycle of output $\text{Y},$ when CLK frequency is $\text{1MHz} \;@\; 50\%$ duty cyle?$500 \;\text{KHz} \;@\; 50\%$ duty cycle$500 \;\text{K...
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