A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is:
Page size of $4KB$. So, offset bits are $12$ bits.
So, remaining bits of virtual address $32 - 12 = 20$ bits will be used for indexing...
Number of sets = 128/4 = 32 (4-way set) => 5 bits.
So, tag bits $= 20 - 5 = 15$ bits.
So, option (C).
@rajat_mahajan this is the how the virtual address will be broken up into:
4KB page defines the offset = 12 bits
32 sets in the TLB defines the set = 5 bits
Remaining 32 - 17 = 15 bits will be used to define tag bits.
here people might not notice u, u can ask as a separate question...