ISRO CSE 2018 | Question: 26

Question

The $FSM$ (Finite State Machine) machine pictured in the figure above

• A. Complements a given bit pattern
• B. Finds $2's$ complement of a given bit pattern
• C. Increments a given bit pattern by $1$ 
• D. Changes the sign bit

Comments

(d) ?

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Despite the error in the FSM, ISRO didn't change the key or discard the question.

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please change the tag from theory of computation to digital circuits

Answer 1

I think there is some error in the diagram. If DFA had been like this :

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Ans:(c) Increments a given bit pattern by 1.

Comments

i can take objection in this question ma'am.bcoz of fig misprint .i marked option A

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If input is 1010, the output is 0110. I don't understand how is this FSM increasing the bit pattern by 1.

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Let's taken an example

input 1011

start from right (1101) and analyze with machine output tends to be 0011 now back to the original way it means 1100.

And if you add 1 with actual input 1011 +1 = 1100.

Answer 2

1. D ans

Comments

What is the order in which we should process our String. Like if String is 1010101 should i start input from left or from right??

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We take always default case i.e, always from left to right scanning