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The $FSM$ (Finite State Machine) machine pictured in the figure above

1. Complements a given bit pattern
2. Finds $2's$ complement of a given bit pattern
3. Increments a given bit pattern by $1$
4. Changes the sign bit

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(d) ?

I think there is some error in the diagram. If DFA had been like this :

.

Ans:(c) Increments a given bit pattern by 1.

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If anything is right this should be the most probable. Otherwise None. :)
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If the input is: 1011.

What will be output?

Since the diagram is ambiguous then it should be reported.
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i can take objection in this question ma'am.bcoz of fig misprint .i marked option A