Consider a processor with a six-stage pipeline: instruction fetch (IF), instruction decode (ID), register fetch (RF), execution (EX), data memory access (DMEM), register writeback (WB). The processor has no branch predictor and the instruction fetcher stalls after fetching a branch instruction until the branch condition and the target are available at the end of the EX stage. Assume that the instruction fetcher can identify branch instructions before they are decoded in the ID stage. If a program has 30% branch instructions, the loss in CPI due to branch-related stalls is ________
