Suppose that a switch is designed to have both input and output $FIFO$ buffering. As packets arrive on an input port they are inserted at the tail of the $FIFO$. The switch then tries to forward the packets at the head of each $FIFO$ to the tail of the appropriate output $FIFO$.
(a) Explain under what circumstances such a switch can lose a packet destined for an output port whose $FIFO$ is empty
