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+3 votes

In 8085 microprocessor, the ISR for handling trap interrupt is at which location?

  1. $3CH$
  2. $34H$
  3. $74H$
  4. $24H$
in CO and Architecture by Boss (30.9k points) | 2.6k views

2 Answers

+13 votes
Best answer

Correct Answer is D.

by Boss (35.7k points)
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@arjun sir and @srestha please verify this.

+9 votes
  • This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.
  • TRAP bas the highest priority and vectored interrupt.
  • TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged.
  • In sudden power failure, it executes a ISR and send the data from main memory to backup memory.
  • The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
  • There are two ways to clear TRAP interrupt.
               1.By resetting microprocessor (External signal)
               2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
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