3 3 votes In 8085 microprocessor, the ISR for handling trap interrupt is at which location? $3CH$ $34H$ $74H$ $24H$ CO & Architecture isro2013 8085-microprocessor non-gatecse + – Misbah Ghaya 4.5k views answer comment Share Follow Print 0 reply Please log in or register to add a comment.
Best answer 12 12 votes Correct Answer is D. rude answered Apr 30, 2016 • selected May 10, 2016 by rude rude comment Share Follow See 1 comment 1 1 comment reply rude commented May 6, 2016 reply Follow flag @arjun sir and @srestha please verify this. 0 0 replyShare Please log in or register to add a comment.
9 9 votes TRAP: This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable. TRAP bas the highest priority and vectored interrupt. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged. In sudden power failure, it executes a ISR and send the data from main memory to backup memory. The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized). There are two ways to clear TRAP interrupt. 1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal) kvkumar answered Jun 29, 2016 kvkumar comment Share Follow 0 reply Please log in or register to add a comment.
