race condition

Question

what is race condition in flip flop  is it the situation when both inputs of SR flip flop is 1 (and hence the invalid state) or something else

Answer 1

When both inputs of a SR flip flop are 0, suppose one input goes high (i.e., 1) immediately. Then, the feedback loop in the flip flop is already busy propagating the previous 0 through both the gates until a stable state is reached. When the other input also goes to 1 immediately, this change also starts to propagate, before the effect of the first change has settled. The effects of the two changes are literally "racing" for priority and it is absolutely not worth guessing as to which one wins. This is called race condition. Thus a R=0,S=0 input is forbidden in a SR flip flop.

Comments

ok  does this race condition exists in other flip flops say in T , D or  JK ?  
or which flip flop are free from race condition

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Of course, race around condition exists in basic JK flip flop as well, the configuration of which is shown below:

When both J and K inputs are 1, the output toggles, i.e., if it was $Q$ earlier, now it becomes $Q'$ and vice-versa. This is because basic JK is a level triggered circuit and so input affects the output as long as CLK is high. So if CLK remains high, output is unstable as it toggles between $Q$ and $Q'$.

Racing can be avoided in JK flip flop if we can ensure that the CLK is high only for a time less than the propagation delay of the gates. This is done by edge triggering.

In the concept of Master Slave JK flip flop, the flip flop is allowed to toggle over one clock period. The configuration is shown below:

Here, when the CLK goes high, the master flip flop is enabled, and the S and R inputs are propagated to the circuit. However, the slave flip flop remains isolated dute to inversion of the CLK. In the next pulse, when CLK goes low, the Master remains locked, whereas the Slave passes the latched information to the outputs $Q$ and $Q'$.

Regarding D flip flop, it is a clocked SR flip flop. The configuration is shown below:

Here, S=D and R=NOT D. Therefore, both inputs are not 1 at the same time. It acts like a memory cell. Whatever is in the Data input (D) is reproduced at the output. It does not suffer forom race-around condition.

The Toggle flip flop (T) is obtained by tying both the inputs J and K high. The operation is positive edge triggered (means, the output changes only when the clock is at its positive edge). When T=0, the output is same as it was before the clock edge (Hold) and when T=1, output toggles (Toggle). It also does not suffer from race-around condition.