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Consider a memory of 8 words per block.If 2 clock cycle are required to transfer address from CPU to main memory, 6 clock cycle to access the first word, 3 clock cycles each for the consecutive words and 2 clock cycles for transferring the words from memory to cache.Then calculate the total clock cycle required to transfer the block with memory interleaving and without interleaving if no of modules are 4.
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w/o interleaving consider the MM as one module

Block size=8 words

2 clock cycle rrquired to sent the address to MM

Considering memory latency first word of the block is accessed in 6 clock cycles. And consecutive words are accessed in 3 clock cycles per word

Data is transferred one word at a time from MM to cache

Total time required to transfer one block from MM to cache=2+6*1+3*7+2*8=45 clock cycles

 

with interleaving

2 clock cycle required to sent the address to MM. now this address will be used by all 4 modules

in the next 6 cycles first 4 words of the block will be loaded into the data buffer registers of each modules [words getting accessed parallely]

for transferring them it'll take 2*4 clock cycles [one word is transferred at a time. word transfer time=2 clock cycles]

Simultaneously the next 4 words will be accessed [it takes 3 clock cycles and this is done parallely while first 4 words are getting transferred]

Again to transfer these 4 words 2*4 cycles are required

so total time required to transfer one block from MM to cache=1+6+4*2+4*2=24 clock cycles

Thus using interleaving total time got almost halved

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