Test by Bikram | Digital Logic | Test 2 | Question: 22

Question

Synchronous counters eliminate the delay problems encountered with asynchronous counters because:

• A. The input clock pulses are applied only to the first and last stages.
• B. The input clock pulses are applied only to the last stage.
• C. The input clock pulses are not used to activate any of the counter stages.
• D. The input clock pulses are applied simultaneously to each stage.

Answer 1

I feel ans is D

Answer 2

In Synchronous Counter, all flip flops are triggered with the same clock simultaneously and Synchronous Counter is faster than the asynchronous counter in operation.

To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state.

So, the correct answer is $(D).$

Reference:

• https://vision.unipv.it/reti-logiche/Chap_05_P3%20Counters.pdf
• https://www.ssucet.org/~jgallaher/download/ETEC2301-ProgrammableLogic/Chapter10-Counters.pdf