# Computer Architecture Doubt

Question

Consider 5 stage pipeline which allow all instructions except branch instruction. Program contain 30% conditional instructions in which of the instructions doesn’t satisfy the condition. When the condition is false then the following instructions are overlapped. Processor stop fetching the following instruction after the branch instruction until target address is available. Target address is available at the end of the pipeline stage. All the stages are perfectly balanced with 20 GHz clock time. The average instruction execution time is ________________ nsec (upto 3 decimal place).

Comments

(1+0.70*4)20 nsec
76nsec??

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@kunal cycle time=1/20GHZ=0.05ns.

and 70% are non conditional they are not overlapped how it creates stalls.// non conditional instruction condition is always true?

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yes i made mistake i cycle time .

u said 70% are non conditional they are not overlapped how it creates stalls. not overlapped means they will create stall .rt??

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Avg inst exen time=(1+no of stalls/inst)*cycle time.

but u take no of stalls/inst=07*4?

here 30%are conditional when condition false they are overlapped .

It is mentioned that 30% conditional are false so they are overlapped and creates a stalls.am i ryt??

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the condition which are overlapped  they will never cause stalls .because they run in pipelined fashion .

moreover stall will occur in that case in which there is no ovelapping .!

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non overlapping means one after another it is like nonpipelined processor.

stalls occur only in pipeline but not in nonpipeline.?