DLC doubts

Question

I have two basic doubts:

1. When Iam required to implement a boolean circuit say $AB'C' + ABC + A'B'C' $ using minimum number of 2*1 MUX, Do i have to minimize this first and then implement or directly ? Do i have to derive a variable in complemented form or assume that it is available if nothing is mentioned?

2. If all the AND gates are replaced by NAND gates, the decoder becomes active LOW ? what does this mean

Comments

For the first i can say that dont minimize the expression as it is better and easy then.

For second , i cant infer what they want to say :(

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logic gate representation of a DEMUX is a obtained by removing OR gate and Joining All inputs as I from a MUX. So, in this representation when all AND are replaced by NAND, does it behave as active LOW?

What is active low and active high btw?

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for the first part : Do i have to derive a variable in complemented form or assume that it is available if nothing is mentioned ?

means using  1 MUX do i have to derive $A'$ or I can directly give it as input to MUX without deriving complement