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In a two-level cache system, the access times of $L_1$ and $L_2$ caches are $1$ and $8$ clock cycles, respectively. The miss penalty from the $L_2$ cache to main memory is $18$ clock cycles. The miss rate of $L_1$ cache is twice that of $L_2$. The average memory access time (AMAT) of this cache system is $2$ cycles. The miss rates of $L_1$ and $L_2$ respectively are

  1. $0.111$ and $0.056$
  2. $0.056$ and $0.111$
  3. $0.0892$ and $0.1784$
  4. $0.1784$ and $0.0892$
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Access time of L1 cache=1 clock cycle

Access time of L2 cache =8 clock cycles

miss penalty of L2 cache to main memory=18 clock cycle

miss rate of L1 cache= 2 * miss rate of L2 cache

AMAT=2 cycles

Avg. Access time of L1 cache= access time of L1 cache+ miss rate of L1 cache=1+2 L2

Avg access time of L2 cache=access time of L2 cache+miss rate of L2 cache* miss penalty of L2 cache=8+18 L2

Acc to given equation  

1+2 L2 +8+18 L2=2

 L2= 0.35

L1=0.70
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