2 votes 2 votes What is the maximum clock frequency at the given circuit can be operated without timing violations? Assume that the Combinational logic delay is 10 ns and the clock duty cycle varies from 40% to 60 %. a) 100 MHz b) 50 MHz c) 40 MHz d) 25 MHz Digital Logic isro-ece digital-logic + – sh!va asked Feb 28, 2017 • edited Mar 10, 2019 by Naveen Kumar 3 sh!va 1.3k views answer comment Share Follow See 1 comment See all 1 1 comment reply Tesla! commented Jul 15, 2017 reply Follow Share Flip flop delay is not given so assuming they are 0 so second flip flop will give stable result after 10 ns due to combinational delay T=10 ns f=100 MHz no i don't know what duty cycle variation do here 0 votes 0 votes Please log in or register to add a comment.
0 votes 0 votes Hope this answer could b helpful Kanie answered Dec 9, 2017 Kanie comment Share Follow See all 0 reply Please log in or register to add a comment.
