Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$. Below table gives the number of clocks required per instruction per stage.
$\begin{array}{|c|c|c|c|c|c|} \hline {} & S1 & S2 & S3 & S4 & S5 \\ \hline I1 & 3 & 1 & 2 & 1 & 2 \\ \hline I2 & 1 & 3 & 1 & 3 & 2 \\ \hline I3 & 1 & 1& 1 & 1 & 2 \\ \hline I4 & 2 & 1 & 2 & 1 &1 \\ \hline \end{array}$
The speed up of the pipeline is approximately ________
