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Recent questions tagged tbb-coa-2

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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 30
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit ... total number of zero address instructions formulated is ________ (put in integers only)
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 29
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is ... $1$0$2048$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 28
Consider the following Micro-operations: ... Memory Buffer RegisterThe given micro-operations describes :Interrupt CycleFetch CycleExecute CycleIndirect Cycle
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 27
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in ... $1$ is ___________ $\%$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 26
Which of the following statements is/are correct about hazards?One way to implement branch prediction is to store the result of a branch condition in a branch target buffer ... is taken.III only II and III onlyI and III onlyI, II, and III
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 25
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let ... memory reference/instruction , average number of stall cycles per instruction will be __________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 24
A byte addressable computer can support maximum of $2^i$ KB memory and has $2^j$ instructions. An instruction involving $2$ operands and $1$ operator needs how many bits ?$3i$2i + j$2i + j + 20$i + j$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 23
Consider a two level memory hierarchy having only one level cache and main memory. Cache and Main memory access times are $20$ ns and $120$ ns/word respectively. ... is referenced $40 \%$ of the times, then average access time is _______ ns
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 22
Suppose that a direct-mapped cache has $2^{10}$ cache lines, with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a ... bytes of space will be required for storing the tags is ________ (put the integer value)
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 21
Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$. Below table gives the number of clocks required ... The speed up of the pipeline is approximately ________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 20
Suppose there are $m$ instructions to be executed in a program. $p$ is the probability that an instruction is a conditional branch instruction, and $q$ is the probability of a successful branch. ... $1 +pq ( n - 1)$ $p - pq$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 19
Consider the following two types of Cache Designs : Cache $1$: It is a direct-mapped cache with eight $1$ - word cache lines. The miss penalty is $8$ clock cycles ... $60$ cyclesCache $1$ spends $56$ cycles and Cache $2$ spends $70$ cycles
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 18
Match the pairs about implementation and addressing modes: ... ), (C-II)(A-III), (B-II), (C-I)(A-II), (B-III), (C-I)
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 17
Consider a pipelined system with these $4$ phases:FI - Fetch instructionDA - Decode and calculate addressFO - Fetch OperandEX- Execute instructionEach phase ... number of clock cycles required to complete the above program is _________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 16
Consider the following statements about the Locality of Reference principle used in the computer memory systems.The principal states that an already accessed memory location ... is/are TRUE?I onlyII onlyII and III onlyI and III only
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 15
Consider a $2$ - way set associative cache memory with $4$ sets and total $8$ cache blocks $(0 - 7)$. Main memory has $64$ blocks $(0 - 63)$. If LRU policy is used for replacement and ... $0 \ 5 \ 9 \ 13 \ 7 \ 0 \ 15 \ 25$2$3$0$1$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 14
Match the following: ... ii-s, iii-q, iv-pi-r, ii-s, iii-p, iv-qi-r, ii-p, iii-s, iv-q
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 13
What is the total number of Read after Write (RAW), Write after Read (WAR) and Write after Write (WAW) dependencies, respectively in the following assembly program? ... $3,1,2$1,2,3$3,2,1$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 12
A $4$ way set associative cache with a size of $32$ KB has line size $16$ Bytes. There is a Byte addressable main memory with a size of $256$ MB, then which ... $ of Cache Memory?$(FCEE90B)16$(FECF10C)16$(CFEE09B)16$(CDDE00B)16$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 11
A control unit has control signals which can be divided into $5$ mutually exclusive groups of $30, 70, 12, 25$ and $23$ control signals ... of bits that are saved using vertical micro-programming over horizontal programming is ___________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 10
Consider the following Program segment for a CPU having three Registers $R1 ,R2 ,R3$ ... executing by the CPU, then the return address saved onto the stack will be _________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 9
A two word instruction is stored in memory at an address designated by symbol $S$. The address field of the instruction (stored at $S+1$) is designated by symbol K. The operand used during the ... M [S ] + (K + 2)$P = (S + 2) + M [ K ]$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 8
A two-dimensional array int $a [32] [32]$ where each element takes $2$ byte, cache size $2^{12}$ bytes and line size is $2^6$ ... initially cache is empty then total number of compulsory cache miss for storing above array is ________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 7
A system is having $4$ way set associative cache of $256$ KB. The cache line size is $8$ words and each word has $32$ bits. Suppose memory addresses ... long. Then number of bits required for the index field of the cache memory is _______
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 6
We want to represent the decimal number $“1000”$ in one’s complement, two’s complement and sign magnitude representations, respectively, which option correctly represent it?$-7,+8,-0$-7,-8,0$-7,-8,-0$+7,+8,-0$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 5
Using Booth’s algorithm for multiplication the multiplier $(- 37)$ will be recorded as:$ -1 +1 0 -1 +1 0 -1$0 +1 0 -1 +1 0 -1$ – 1 0 +1 -1 +1 0 -1$+1 \ 0 \ 0 -1 +1 0 -1$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 4
Consider a computer system that has a cache with $512$ blocks, each of which can store $32$ bytes of data. All addresses are byte addresses.Then to which cache line will the ... text{DBA, 3C}$\text{1DA, 1D}$\text{1DF, 1F}$\text{1CF, 3E}$
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 3
A processor is having an instruction which can move a string of Bytes from one memory location to another. The fetching and decoding of the instruction takes ... of $64$ Bytes then to execute the instruction, time required is ________ns
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 2
$16$kB cache with line size $64$B uses $4$ – way set associative mapping. Main memory is $8$ MB and byte addressable. The size of extra space needed for storing tag information in bytes is _________
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Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 1
A DMA module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16$ KB/s. The processor is fetching instructions at the ... by which the processor will be slowed down due to the DMA activity is ______
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