Dark Mode

Recent questions tagged instruction-format

0 votes

1 answer

1

instruction-format
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then how many two instructions are possible at maximum?

someshawasthi asked in CO and Architecture Oct 27, 2022

by someshawasthi

196 views

0 votes

0 answers

2

Vishvadeep sir DPP, Instructions
Disadvantages of using 2-address instruction in place of 1-address instructions is/are? More memory required for program Larger sized instructions More number of instructions only 1 only 1 & 3 only 2 all 1,2 and 3

kanakjyoti asked in CO and Architecture Sep 1, 2022

75 views

1 vote

1 answer

3

Consider a system which supports only 1-address type instructions. The size of memory the system has is 2^m KB. The system supports ' i ' distinct instructions. The length of an instruction is ____ Bytes?

isriram asked in CO and Architecture Jun 9, 2022

324 views

1 vote

0 answers

4

GeeksForGeeks AIM 2 - instruction format
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based ... . How many bits are in address selection field, address field and the size of control memory in words respectively?

atulcse asked in CO and Architecture Jan 15, 2022

357 views

1 vote

2 answers

5

made easy test series - instruction format
Consider a hypothetical CPU which supports 16-bit instruction, 64 registers and 1 KB memory space. If there exist 12 2-address instructions which use register references and 12 1-address memory reference instructions then how many 0-address instructions are possible?

atulcse asked in CO and Architecture Jan 13, 2022

394 views

0 votes

1 answer

6

Computer Organization, Instruction Set Architecture, Gateforum
Consider a system with 16 Registers(Ro,R1,...R8).An instruction SUB Ro,R1 , which is two bytes long,what is the space assigned to the opcode field (in bits) ?

Swarnava Bose asked in CO and Architecture Oct 21, 2021

by Swarnava Bose

333 views

3 votes

1 answer

7

NIELIT 2017 OCT Scientific Assistant A (IT) - Section C: 8
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

1.2k views

1 vote

2 answers

8

NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

1.2k views

4 votes

1 answer

9

NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 3
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

527 views

3 votes

5 answers

10

NIELIT 2017 DEC Scientist B - Section B: 6
A stack organized computer has which of the following instructions? zero-address one-address two-address three-address

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

2.0k views

0 votes

3 answers

11

NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

3.7k views

0 votes

1 answer

12

NIELIT 2017 DEC Scientist B - Section B: 49
Which of the following is false? Interrupts which are initiated by an instruction are software interrupts When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer A micro program which is written as $0$’s and $1$’s is a binary micro program None of the options

Lakshman Patel RJIT asked in CO and Architecture Mar 30, 2020

by Lakshman Patel RJIT

1.1k views

21 votes

6 answers

13

GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.

Arjun asked in CO and Architecture Feb 12, 2020

by Arjun

23.1k views

2 votes

1 answer

14

ISRO2020-49
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called True dependency Anti-dependency Output dependency Control Hazard

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

1.7k views

0 votes

0 answers

15

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 6 (Page No. 81)
Instructions related to accessing I/O devices are typically privileged instructions, that is, they can be executed in kernel mode but not in user mode. Give a reason why these instructions are privileged.

Lakshman Patel RJIT asked in Operating System Oct 23, 2019

by Lakshman Patel RJIT

135 views

4 votes

3 answers

16

Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

Rishav Chetan asked in CO and Architecture Jan 19, 2019

by Rishav Chetan

742 views

2 votes

1 answer

17

MadeEasy Subject Test 2019: CO & Architecture- Instruction Format
In an 16 bit instruction the size of address field is 7 bits. The computer uses expanding opcode technique.It has 2, two address instructions and 250 one address instruction. How many Zero address instructions can be formulated ? 5120 15304 768 1024 0

Na462 asked in CO and Architecture Jan 16, 2019

by Na462

801 views

1 vote

0 answers

18

Testbook Test Series: CO & Architecture - Instruction Format
A processor has $128$ distinct instructions. A $24-$bit instruction word has an opcode, register, and operand.The number of bits available for the operand field is $7.$The maximum possible value of the general-purpose register is _________

Lakshman Patel RJIT asked in CO and Architecture Dec 23, 2018

by Lakshman Patel RJIT

708 views

0 votes

2 answers

19

AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.

shaz asked in CO and Architecture Dec 13, 2018

by shaz

548 views

2 votes

0 answers

20

MadeEasy Test Series: CO & Architecture - Instruction Format
How they have calculated the memory address part?

Gupta731 asked in CO and Architecture Nov 15, 2018

846 views

1 vote

2 answers

21

MadeEasy Test Series: CO & Architecture - Instruction Format
How will this question be solved?

nephron asked in CO and Architecture Oct 24, 2018

598 views

0 votes

2 answers

22

Number of bits - Instruction format
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 ... and an address part. How many bits are there in the operation code, the register code part, and the address part respectively?

Balaji Jegan asked in CO and Architecture Oct 16, 2018

by Balaji Jegan

6.1k views

5 votes

1 answer

23

Addressing Mode
Consider we have an instruction Load 1000. Given Memory and Register R1 as Follows. What is the actual value Loaded in the accumulator ? A. 1000 1400 1300 1000 B. 1400 1300 1000 1000 C. 1000 1300 1400 1000 D. 1300 1000 1400 1000

Na462 asked in CO and Architecture Oct 12, 2018

by Na462

2.5k views

1 vote

1 answer

24

Computer Organization
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size I1 MOV CX,0005 ; CX ← 0005 I2 MOV BX,OFF7H ; BX ← OFF7H I3 MOV AX,OBCAH ; AX ← OBCAH I4 OR BX,AX ; BX ← ... 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU?

Sumit Singh Chauhan asked in CO and Architecture Sep 2, 2018

by Sumit Singh Chauhan

1.7k views

4 votes

1 answer

25

Computer Organization
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent one of 7 addressing modes and memory address field. How many instructions the system supports when a 32- bit instruction is placed in the one memory cell.

Sumit Singh Chauhan asked in CO and Architecture Sep 2, 2018

by Sumit Singh Chauhan

9.3k views

2 votes

3 answers

26

Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?

srestha asked in CO and Architecture Jun 7, 2018

1.8k views

2 votes

3 answers

27

ISRO2018-6
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code: Multiply $E$ by $0.5$ to get $F$ Add $A$ and $B$ to get $E$ Add $B$ with $0.5$ to get ... sequence of execution is valid? B, C, D, A, E C, B, E, A, D A, B, C, D, E E, D, C, B, A

Arjun asked in CO and Architecture Apr 22, 2018

by Arjun

2.4k views

1 vote

5 answers

28

ISRO2018-31
A byte addressable computer has a memory capacity of $2$^{m}$KB$ ($k$ bytes) and can perform $2$^{n}$ operations. An instruction involving $3$ operands and one operator needs maximum of: $3m$ bits $3m + n$ bits $m + n$ bits none of the above

Arjun asked in CO and Architecture Apr 22, 2018

by Arjun

3.0k views

Page:

Recent questions tagged instruction-format