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Recent questions tagged instruction-format
1
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No of 1 Address 2 Address 0 Address Instructions Practice
I have seen lots of questions like this : A load-store architecture in which memory operation applied only on LOAD and STORE instructions and other all operations are REG-REG instructions. Assume three address architecture. Find the minimum number of ... 3AI: 7 2AI:12 1AI:15 0AI:16 Please comment if anything wrong!!!
squirrel69
asked
in
CO and Architecture
Nov 5, 2023
by
squirrel69
226
views
machine-instruction
instruction-format
instruction-execution
1
vote
2
answers
2
GATE@Zeal COA Topic Test
saurabh0709
asked
in
CO and Architecture
Sep 27, 2023
by
saurabh0709
281
views
numerical-answers
test-series
co-and-architecture
instruction-format
1
vote
2
answers
3
Ace Test Series | COA | Addressing
A system support zero address, one address & two address instructions. Let 16-bit instruction is stored in 128-word memory. Identify the correct among the following. (A) 16K zero address, 128-one address, 2-two address instructions (B) 256 K ... -zero address instructions (C) 28 K zero address, 2-two address, 32-one address instructions (D) None of the above
none30
asked
in
CO and Architecture
Sep 5, 2023
by
none30
342
views
co-and-architecture
ace-test-series
instruction-format
2
votes
1
answer
4
Unacademy Computer Organization and Architecture Workbook
consider a system which supports 2-address, 1-address and 0-address instruction. the system has 'i' bits addresses. if there are 'x' 2-addresses instructions and 'y' 1-addresses. then what is maximum number of 0-addresses instructions supported by system
lovish_bhatia
asked
in
CO and Architecture
Aug 14, 2023
by
lovish_bhatia
344
views
computer-architecture
instruction-format
0
votes
1
answer
5
Self Doubt Randomly found on Internet
Consider a hypothetical processor which supports 2-address instructions and 1-address instructions both. The system supports 32-bits fixed length instructions. The system has 16KB byte addressable memory. Minimum number of instructions supported by processor is
deba1014
asked
in
CO and Architecture
Aug 11, 2023
by
deba1014
286
views
co-and-architecture
computer-architecture
instruction-format
0
votes
0
answers
6
Self Doubt Random found on Internet
Consider a system which supports 2-address and 1-address instructions both. System has 20-bits instructions and 7-bits addresses then which of the following is/are the number of 1-address instructions possible for the system?
deba1014
asked
in
CO and Architecture
Aug 11, 2023
by
deba1014
354
views
computer-architecture
co-and-architecture
instruction-format
0
votes
1
answer
7
Self Doubt Random Found on Internet
Consider a CPU which supports fixed length instructions. For this CPU a compiler generates 175 instructions for a user program. All the instructions are stored in the memory in byte aligned fashion, occupying a total of 525 bytes space in memory. The minimum possible length of one instruction for the CPU is _______ bits?
deba1014
asked
in
CO and Architecture
Aug 10, 2023
by
deba1014
455
views
computer-architecture
co-and-architecture
instruction-format
0
votes
1
answer
8
instruction-format
Assume an instruction set that uses a fixed 31 bit instruction length. Operand specifies are 4 bits in length. If there are m-three operand instructions in total, then how many two instructions are possible at maximum?
someshawasthi
asked
in
CO and Architecture
Oct 27, 2022
by
someshawasthi
491
views
co-and-architecture
instruction-format
0
votes
0
answers
9
Vishvadeep sir DPP, Instructions
Disadvantages of using 2-address instruction in place of 1-address instructions is/are? More memory required for program Larger sized instructions More number of instructions only 1 only 1 & 3 only 2 all 1,2 and 3
kanakjyoti
asked
in
CO and Architecture
Sep 1, 2022
by
kanakjyoti
232
views
co-and-architecture
instruction-format
1
vote
1
answer
10
Consider a system which supports only 1-address type instructions. The size of memory the system has is 2^m KB. The system supports ' i ' distinct instructions. The length of an instruction is ____ Bytes?
isriram
asked
in
CO and Architecture
Jun 9, 2022
by
isriram
1.1k
views
computer-architecture
instruction-format
1
vote
0
answers
11
GeeksForGeeks AIM 2 - instruction format
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based ... . How many bits are in address selection field, address field and the size of control memory in words respectively?
atulcse
asked
in
CO and Architecture
Jan 15, 2022
by
atulcse
587
views
co-and-architecture
instruction-format
1
vote
2
answers
12
made easy test series - instruction format
Consider a hypothetical CPU which supports 16-bit instruction, 64 registers and 1 KB memory space. If there exist 12 2-address instructions which use register references and 12 1-address memory reference instructions then how many 0-address instructions are possible?
atulcse
asked
in
CO and Architecture
Jan 13, 2022
by
atulcse
598
views
co-and-architecture
instruction-format
made-easy-test-series
0
votes
1
answer
13
Computer Organization, Instruction Set Architecture, Gateforum
Consider a system with 16 Registers(Ro,R1,...R8).An instruction SUB Ro,R1 , which is two bytes long,what is the space assigned to the opcode field (in bits) ?
Swarnava Bose
asked
in
CO and Architecture
Oct 21, 2021
by
Swarnava Bose
874
views
numerical-answers
co-and-architecture
instruction-format
3
votes
1
answer
14
NIELIT 2017 OCT Scientific Assistant A (IT) - Section C: 8
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii
Lakshman Bhaiya
asked
in
CO and Architecture
Apr 1, 2020
by
Lakshman Bhaiya
1.6k
views
nielit2017oct-assistanta-it
co-and-architecture
instruction-format
machine-instruction
1
vote
2
answers
15
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
Lakshman Bhaiya
asked
in
CO and Architecture
Apr 1, 2020
by
Lakshman Bhaiya
2.0k
views
nielit2017oct-assistanta-it
co-and-architecture
machine-instruction
instruction-format
3
votes
1
answer
16
NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 3
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii
Lakshman Bhaiya
asked
in
CO and Architecture
Apr 1, 2020
by
Lakshman Bhaiya
836
views
nielit2017oct-assistanta-cs
co-and-architecture
instruction-format
machine-instruction
3
votes
5
answers
17
NIELIT 2017 DEC Scientist B - Section B: 6
A stack organized computer has which of the following instructions? zero-address one-address two-address three-address
Lakshman Bhaiya
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Bhaiya
2.8k
views
nielit2017dec-scientistb
co-and-architecture
instruction-format
1
vote
3
answers
18
NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor? Large number of addressing modes. Uniform instruction set. (i) Only (ii) Only Both (i) and (ii) None of the options
Lakshman Bhaiya
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Bhaiya
4.4k
views
nielit2017dec-scientistb
co-and-architecture
addressing-modes
instruction-format
0
votes
1
answer
19
NIELIT 2017 DEC Scientist B - Section B: 49
Which of the following is false? Interrupts which are initiated by an instruction are software interrupts When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer A micro program which is written as $0$’s and $1$’s is a binary micro program None of the options
Lakshman Bhaiya
asked
in
CO and Architecture
Mar 30, 2020
by
Lakshman Bhaiya
1.7k
views
nielit2017dec-scientistb
co-and-architecture
interrupts
instruction-format
24
votes
6
answers
20
GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
Arjun
asked
in
CO and Architecture
Feb 12, 2020
by
Arjun
28.5k
views
gatecse-2020
co-and-architecture
numerical-answers
instruction-format
machine-instruction
2-marks
2
votes
1
answer
21
ISRO2020-49
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called True dependency Anti-dependency Output dependency Control Hazard
Satbir
asked
in
CO and Architecture
Jan 13, 2020
by
Satbir
2.4k
views
isro-2020
co-and-architecture
instruction-format
normal
0
votes
0
answers
22
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 6 (Page No. 81)
Instructions related to accessing I/O devices are typically privileged instructions, that is, they can be executed in kernel mode but not in user mode. Give a reason why these instructions are privileged.
Lakshman Bhaiya
asked
in
Operating System
Oct 23, 2019
by
Lakshman Bhaiya
190
views
tanenbaum
operating-system
instruction-format
descriptive
4
votes
3
answers
23
Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?
Rishav Chetan
asked
in
CO and Architecture
Jan 19, 2019
by
Rishav Chetan
1.1k
views
machine-instruction
instruction-format
computer-architecture
2
votes
1
answer
24
MadeEasy Subject Test 2019: CO & Architecture- Instruction Format
In an 16 bit instruction the size of address field is 7 bits. The computer uses expanding opcode technique.It has 2, two address instructions and 250 one address instruction. How many Zero address instructions can be formulated ? 5120 15304 768 1024 0
Na462
asked
in
CO and Architecture
Jan 16, 2019
by
Na462
954
views
co-and-architecture
instruction-format
made-easy-test-series
0
votes
1
answer
25
CO DOUBT
Certain CPU uses expanding op-code . It has 16 bit instructions with 6-bit addresses . It has maximum 192 one-address Instructions. Then number of 2-addresses instructions are supported by the system is __________________
Magma
asked
in
CO and Architecture
Jan 8, 2019
by
Magma
350
views
co-and-architecture
instruction-format
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