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Recent questions tagged instruction-format
3
3 votes
5
5 answers
4.2k
4.2k views
NIELIT 2017 DEC Scientist B - Section B: 6
A stack organized computer has which of the following instructions?zero-addressone-addresstwo-addressthree-address
admin
4.2k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017dec-scientistb
co-and-architecture
instruction-format
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1
1 vote
4
4 answers
5.3k
5.3k views
NIELIT 2017 DEC Scientist B - Section B: 40
Which of the following is/are not features of RISC processor?Large number of addressing modes.Uniform instruction set.(i) Only(ii) OnlyBoth (i) and (ii)None of the option...
admin
5.3k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017dec-scientistb
co-and-architecture
addressing-modes
instruction-format
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0
0 votes
2
2 answers
2.5k
2.5k views
NIELIT 2017 DEC Scientist B - Section B: 49
Which of the following is false?Interrupts which are initiated by an instruction are software interruptsWhen a subroutine is called, the address of the instruction follow...
admin
2.5k
views
asked
Mar 30, 2020
CO & Architecture
nielit2017dec-scientistb
co-and-architecture
interrupts
instruction-format
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–
66
66 votes
9
answers
9 answers
45.8k
45.8k views
GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a re...
Arjun
45.8k
views
asked
Feb 12, 2020
CO & Architecture
gatecse-2020
co-and-architecture
numerical-answers
instruction-format
machine-instruction
two-marks
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5
5 votes
1
1 answer
4.0k
4.0k views
ISRO CSE 2020 | Question: 49
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency calledTrue dependencyAnti-dependencyOutput dependenc...
Satbir
4.0k
views
asked
Jan 13, 2020
CO & Architecture
isro-2020
co-and-architecture
instruction-format
normal
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–
0
0 votes
0
0 answers
360
360 views
Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 6 (Page No. 81)
Instructions related to accessing I/O devices are typically privileged instructions, that is, they can be executed in kernel mode but not in user mode. Give a reason why ...
admin
360
views
asked
Oct 23, 2019
Operating System
tanenbaum
operating-system
instruction-format
descriptive
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–
4
4 votes
3
3 answers
2.2k
2.2k views
Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two addre...
Rishav Chetan
2.2k
views
asked
Jan 19, 2019
CO & Architecture
machine-instruction
instruction-format
co-and-architecture
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2
2 votes
1
1 answer
1.6k
1.6k views
MadeEasy Subject Test 2019: CO & Architecture- Instruction Format
In a 16-bit instruction format, the size of the address field is 7 bits. The computer uses an expanding opcode technique. It has 2, two address instructions and 250 one a...
Na462
1.6k
views
asked
Jan 16, 2019
CO & Architecture
co-and-architecture
instruction-format
made-easy-test-series
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0
0 votes
1
1 answer
1.0k
1.0k views
CO DOUBT
Certain CPU uses expanding op-code . It has 16 bit instructions with 6-bit addresses . It has maximum 192 one-address Instructions.Then number of 2-addresses instructions...
Magma
1.0k
views
asked
Jan 8, 2019
CO & Architecture
co-and-architecture
instruction-format
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–
1
1 vote
0
0 answers
3.3k
3.3k views
Testbook Test Series: CO & Architecture - Instruction Format
A processor has $128$ distinct instructions. A $24-$bit instruction word has an opcode, register, and operand.The number of bits available for the operand field is $7.$Th...
Lakshman Bhaiya
3.3k
views
asked
Dec 23, 2018
CO & Architecture
testbook-test-series
co-and-architecture
instruction-format
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0
0 votes
2
2 answers
1.1k
1.1k views
AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
shaz
1.1k
views
asked
Dec 13, 2018
CO & Architecture
instruction-format
machine-instruction
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–
2
2 votes
0
0 answers
1.8k
1.8k views
MadeEasy Test Series: CO & Architecture - Instruction Format
How they have calculated the memory address part?
Gupta731
1.8k
views
asked
Nov 15, 2018
CO & Architecture
made-easy-test-series
co-and-architecture
instruction-format
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–
1
1 vote
2
2 answers
1.8k
1.8k views
MadeEasy Test Series: CO & Architecture - Instruction Format
How will this question be solved?
nephron
1.8k
views
asked
Oct 24, 2018
CO & Architecture
co-and-architecture
instruction-format
made-easy-test-series
numerical-answers
+
–
0
0 votes
2
2 answers
8.3k
8.3k views
Number of bits - Instruction format
A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit,...
Balaji Jegan
8.3k
views
asked
Oct 16, 2018
CO & Architecture
co-and-architecture
instruction-format
numerical-answers
+
–
1
1 vote
1
1 answer
3.3k
3.3k views
Computer Organization
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit sizeI1 MOV CX,0005 ; CX ← 0005I2 MOV BX,OFF7H...
Sumit Singh Chauhan
3.3k
views
asked
Sep 2, 2018
CO & Architecture
co-and-architecture
machine-instruction
instruction-format
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7
7 votes
2
2 answers
17.2k
17.2k views
Computer Organization
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent on...
Sumit Singh Chauhan
17.2k
views
asked
Sep 2, 2018
CO & Architecture
co-and-architecture
machine-instruction
instruction-format
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–
2
2 votes
3
answers
3 answers
3.3k
3.3k views
Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate...
srestha
3.3k
views
asked
Jun 7, 2018
CO & Architecture
machine-instruction
instruction-format
co-and-architecture
+
–
1
1 vote
2
2 answers
1.7k
1.7k views
Ace Test Series 2019: Number Of Zero Address Instructions
A system has 16 bits instruction that support zero address, one addressand two address instructions Assume each address field size is 5 bits itis designed for supporting ...
Kartavya Kothari
1.7k
views
asked
May 11, 2018
CO & Architecture
ace-test-series
co-and-architecture
instruction-format
+
–
4
4 votes
3
3 answers
4.7k
4.7k views
ISRO CSE 2018 | Question: 6
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execut...
Arjun
4.7k
views
asked
Apr 22, 2018
CO & Architecture
isro2018
co-and-architecture
instruction-format
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–
4
4 votes
5
5 answers
8.1k
8.1k views
ISRO CSE 2018 | Question: 31
A byte addressable computer has a memory capacity of $2$$^{m}$$KB$ ($k$ bytes) and can perform $2$$^{n}$ operations. An instruction involving $3$ operands and one operato...
Arjun
8.1k
views
asked
Apr 22, 2018
CO & Architecture
isro2018
co-and-architecture
instruction-format
+
–
106
106 votes
8
answers
8 answers
42.7k
42.7k views
GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{...
gatecse
42.7k
views
asked
Feb 14, 2018
CO & Architecture
gatecse-2018
co-and-architecture
machine-instruction
instruction-format
numerical-answers
two-marks
+
–
5
5 votes
1
1 answer
1.1k
1.1k views
Addresing mode
Please Explain in detail
Shubham Kumar Gupta
1.1k
views
asked
Jan 16, 2018
CO & Architecture
addressing-modes
co-and-architecture
instruction-format
+
–
1
1 vote
1
1 answer
896
896 views
zero address instruction
In a 16-bit computer instruction format, the size of the address field is 5 bits. The computer uses an expanding opcode technique. It has 2 two-address instructions and 1...
Jaspreet Kaur Bains
896
views
asked
Jan 2, 2018
CO & Architecture
co-and-architecture
instruction-format
+
–
4
4 votes
2
answers
2 answers
3.2k
3.2k views
no of 0 address instructions
A hypothetical processor supports two-address, one-address and zero-address instructions. It has a 256 word memory and each instruction is 19 bits long. If there are 4 tw...
Parshu gate
3.2k
views
asked
Nov 16, 2017
CO & Architecture
co-and-architecture
instruction-format
+
–
2
2 votes
1
answers
1 answer
2.2k
2.2k views
addressing mode reduces no of bits?
computer uses addressing modes to reduce the number of bits in the addressing field of the instructionCan someone please explain how this statement is true? PLEASEExample...
Rishabh Gupta 2
2.2k
views
asked
Nov 5, 2017
CO & Architecture
addressing-modes
instruction-format
+
–
1
1 vote
1
1 answer
3.4k
3.4k views
Register Direct and Indirect Addressing Mode
I am watching IIT Madras lecture of Addressing mode, in that Prof take an example, in which we have a register r0 = 1000Link:- https://www.youtube.com/watch?v=p9wxyIx-j-c...
Shubhanshu
3.4k
views
asked
Sep 26, 2017
CO & Architecture
addressing-modes
co-and-architecture
instruction-format
+
–
14
14 votes
5
answers
5 answers
20.7k
20.7k views
#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word.Q...
junaid ahmad
20.7k
views
asked
Jul 24, 2017
CO & Architecture
co-and-architecture
cache-memory
machine-instruction
instruction-format
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–
2
2 votes
1
1 answer
2.0k
2.0k views
Addressing mode
Self reallocating code required for displacement addressing mode.How ?Please someone explain this concept.
set2018
2.0k
views
asked
Jul 17, 2017
CO & Architecture
self-doubt
co-and-architecture
addressing-modes
instruction-format
+
–
0
0 votes
1
answers
1 answer
768
768 views
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 30
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed i...
Bikram
768
views
asked
May 27, 2017
CO & Architecture
tbb-coa-2
numerical-answers
co-and-architecture
instruction-format
+
–
0
0 votes
1
answers
1 answer
940
940 views
Test by Bikram | Mock GATE | Test 4 | Question: 50
A computer has $170$ different operations. Memory is word addressable where word size is $4$ bytes and each instruction requires one word. All instructions have two addre...
Bikram
940
views
asked
May 14, 2017
CO & Architecture
tbb-mockgate-4
co-and-architecture
instruction-format
+
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